32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Dolphin Integration Announces their new generation of CODEC providing a Signal to Noise Ratio of 100 dB
A real 100 dB CODEC per the “Practical benchmark”, at no compromise of power consumption, silicon area and yield, was the true challenge now faced successfully.
shCODlp-100.01 is the best contributor to the Return-On-Investment of a SoC:
- a silicon area of 4.2 mm2 for the whole CODEC at no extra fabrication cost: 5 metal layers over a logic process at 0.13 µm
- SNR is guaranteed at ViC level with complete integration guidelines, including characterization to resilience from Rest-of-SoC noise
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Dolphin Design Hot IP
Related News
- Dolphin Integration announces the availability at 40 nm of low-power audio codec with SNR of 100 dB
- Dolphin Integration lightens CD10ACN50, a high-performance 100 dB Audio CODEC in Fujitsu Microelectronics' 90 nm
- More configurations for the audio CODEC from Dolphin Integration proven with 100 dB
- Dolphin Integration offers the highest performances for an audio CODEC of the Xenon family: up to 106 dB of SNR at 65 nm.
- The first configuration of Dolphin Integration stars an audio converter at 40 nm LP to a high SNR of 100 dB
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