Infineon Technologies Announces New Version Of TriCore[tm] Unified Processor Architecture for Embedded Devices
Enhanced Core Architecture Includes Memory Management Unit To Support New Operating Systems, Additional Features To Support Parallel Computing
Munich, Germany/San Jose (Embedded Processor Forum), June 13, 2000 - Infineon Technologies (FSE/NYSE:IFX) today introduced Version 1.3 of its TriCore[tm] Unified Processor Core architecture. In addition to a higher operating frequency than earlier versions, the new core includes a high-speed local memory bus to support increased levels of parallel compute operations, and an enhanced co-processor bus interface. Additionally, the core features an integrated Memory Management Unit (MMU) to support advanced operating systems, such as EPOC32, Linux, and Windows[tm] CE.
When manufactured in Infineon Technologies' proven 0.18-micron process technology, this implementation of the award winning single-core compute engine operates at frequencies of 166 - 200 MHz. In embedded system applications that require both real-time microcontroller (MCU) and Digital Signal Processor (DSP) functionality, the core provides raw processing rates of up to 250 MIPS when operating at 166 MHz.
New application specific standard products (ASSPs) based on Version 1.3 of the TriCore Unified Processor architecture, including products utilizing the integrated MMU, are expected to sample late in 2000. Infineon also will license the core architecture as a part of the company's open processor IP policy.
"This new version of the TriCore Unified Processor architecture marks an important step in the development of the embedded control portfolio of Infineon," said Tony Webster, vice president of the Cores & Modules Group at Infineon Technologies. "With the addition of an MMU, we can now support applications running on all of the major embedded operating systems. The improved system performance of the architecture enhances our position as a top-tier provider of advanced core and processor system architectures across the entire spectrum of embedded and DSP systems design."
Broadened Scope of Applications
The TriCore Unified Processor architecture is well suited for applications that previously required separate MCU and DSP components. It has already been implemented in processors for industrial computer control, automotive engine controls, and telecommunications. With the addition of the MMU, additional application categories and markets are now open to solutions based on the architecture.
The compact size of the core also supports very high-levels of integration in single-chip systems. In a presentation at the Embedded Processor Forum, in San Jose, Calif., Infineon described the parallel computing features of the core technology, as implemented in Version 1.3, and described how the core could be used to create a single-chip multiprocessor for very high-performance embedded applications.
The Version 1.3 MicroProcessor System announced this week is a 5.9 million transistor design that integrates the compute engine, a total of 64 Kbytes of memory, MMU, co-processor interface, 64-bit local memory bus, power management and on-chip debug capability. With a CPU die area less than 3 mm2, it is feasible to integrate multiple TriCore Version 1.3 Unified Processor cores on a single-chip, while maintaining low power consumption as a result of the 166 MHz operating frequency. A hypothetical four-core chip, for example, would achieve raw processing performance of up to 1000 MIPS.
Development Tool Compatibility and Support
As with previous versions of TriCore Unified Processor architecture, complete development tools from several leading third-party vendors are starting to become available for Version 1.3. All tools that currently support Version 1.2 are compatible with Version 1.3. Development tools from TASKING offer full support for Version 1.3 (MMU + additional new features), and other tool vendors, including Green Hills Software, Inc., will provide support in the near future.
The parallel computing performance of the TriCore Unified Processor architecture is based on its use of a single instruction set to execute both control and DSP tasks on a single processing engine. The superscalar pipeline implementation of the CPU enables execution of up to three instructions per cycle, and a hardware-supported task-switching mechanism enables fast interrupt handling, which is critical for real-time performance. This allows designers to dynamically allocate the available processing resources to either DSP or control tasks, eliminating the inherent waste associated with fixed hardware partitioning that often leaves relatively large portions of the processing power idle at any given time.
A key feature of the TriCore Unified Processor architecture is the availability of an integrated development environment and system design tool chain, supporting concurrent development of both control and DSP application code using a common tool set. This is important to developers working to meet the compressed system design timetables that are increasingly common in development of embedded products.
In independent benchmark tests during 1999, the architecture was compared both to stand-alone microcontroller and DSP devices. It was demonstrated that the TriCore Unified Processor delivers superior performance in DSP tasks, while achieving the memory usage and code size advantages of best in class MCUs. The recently published results of tests conducted by EEMBC, a broadly supported industry group developing comprehensive applications tests for embedded devices, also concluded that a TriCore-based general purpose CPU achieves excellent performance on a cycle-by-cycle basis when compared to alternative processor architectures.
Further information about TriCore is available at www.infineon.com/tricore.
Infineon Technologies AG, Munich, Germany, offers semiconductor solutions for applications in the wireless and wired communications markets, for the automotive and industrial sectors, for security systems and chip cards as well as memory products. With a global presence, Infineon operates in the US from San Jose, CA, and in the Asia-Pacific region from Singapore. In the fiscal year 1999 (ending September), the company achieved sales of Euro 4.24 billion (US $ 4.51 billion) with about 26,000 employees worldwide. The company is listed on the main market segment (Amtlicher Handel) of the Frankfurt Stock Exchange and at the New York Stock Exchange. Further information is available at www.infineon.com.
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Any statements in this document that are not historical facts are forward-looking statements that involve risks and uncertainties; actual results may differ from the forward-looking statements. Infineon Technologies undertakes no obligation to publicly release the results of any revisions to these forward-looking statements that may be made to reflect events or circumstances after the date hereof or to reflect the occurrence of unanticipated events.