Update: Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation (Oct. 17, 2017)
January 23, 2007, Ottawa, ON: Sidense, leading developer of non volatile memory IP cores will be exhibiting its leading edge technology at the 2007 EDS Fair on January 25th and 26th at the Pacifico Yokohama in Yokohama, Japan. Sidense is greeting customers at Booth #217.
"This is an exciting time for our company and we are looking forward to exhibiting at the EDS Fair Japan. We already have customer traction in the Japanese market and we expect to be meeting several new potential customers there"' said Xerxes Wania, President and CEO of Sidense.
The EDSFair is one of the three largest trade shows in the world in the field of semiconductor and electronic system design, along with the US Design Automation Conference (DAC) and Design, Automation Test in Europe (DATE).
Sidense is introducing several new products in different technology nodes. Currently, technology is available in TSMC, SMIC, Chartered and UMC 180, 130, and 90nm processes and in the future additional process nodes including 65 and 45nm will be available in several foundries and Integrated Device Manufacturers (IDMs).
Sidense provides secure, dense and reliable non-volatile memory IP cores for use in standard logic CMOS processes. No additional masks or process steps are required. Sidense's proprietary 1T-FuseTM technology is available in 0.18um, 0.13um, 0.11um, 90nm, and 65nm from the leading foundries. Ideal applications include electrical fuse replacement, flash and mask programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI and digital rights management (DRM). The company has offices in Mississauga and Ottawa, Canada and sales offices in San Francisco, CA and Tokyo, Japan. For more information, visit www.sidense.com.