Plurality Ltd. Announces its New HyperCore Architecture Line (HAL) of Multicore Processors

The completion of Plurality’s proof of concept represents a breakthrough in multicore architecture.
The solution is currently available as an evaluation and development kit and will be soon followed by a 64-core commercial chip.

Netanya, Israel -- January 24, 2007 -- Plurality Ltd. announced today the availability of its HyperCore Processor, the first solution to emerge from its HyperCore Architecture Line (HAL) of multicore processors, following completion of its proof of concept.

The design was implemented on an Altera Stratix® II-180 FPGA and incorporates 16 32-bit RISC cores managed by a high flow rate Synchronizer/Scheduler, sharing a common memory. The FPGA design comprises a 4-Mbit data cache, a 2-Mbit instruction cache, 4 32-bit multipliers and 4 64-bit dividers.

“The success of our proof of concept shows that Plurality’s unique, patented technology is able to provide the much expected performance promised by parallel processors, while offering the programmability of a serial processor,” said Moshe Serfaty, Chairman and CEO. “We are now eager to partner with customers, in various industries, interested in employing the most advanced and programmable multicore solution.”

The FPGA design is now being offered to Plurality’s customers on a PCI/PCIe board, from GiDEL’s family of PROC Boards™, as an evaluation and development kit. The board contains several configurable add-ons such as video and network interfaces, external IO, and others.

Additionally, Plurality offers a cycle-accurate graphic simulator for HyperCore Processors of up to 256 cores, which represents an extremely powerful development and debugging tool.

Using Plurality’s unique Task Oriented Programming model, customers will be able to easily transport their applications into a powerful multicore system using tools and a development environment they already are familiar with, and very similar to the ones used to program a serial processor. The evaluation kit enables compiling, running and debugging the code. Once this is achieved, the code can be seamlessly executed by any of Plurality’s multicore configurations, without the need to reprogram applications as core capacity increases.

For volume production of its first version of HyperCore Processors, Plurality plans to use eASIC®’s Nextreme™, 90nm Structured ASIC family, with 64 32-bit RISC cores running at 150MHz. Initial delivery is scheduled for Q3 2007.

Plurality’s architecture is extremely scalable and will soon allow the introduction of more powerful HyperCore Processors reaching up to 256 cores.

About Plurality

Plurality Ltd. is the provider of the HyperCore Processor, a viable multicore processing solution that greatly speeds up complex processing and applications. The HyperCore Processor is a scalable, easily programmable, general-purpose, multicore processor that addresses the performance required by modern algorithms and applications while exploiting their inherent parallelism.
www.plurality.com