Integrated platform combines enhanced DSP blocks for parallel processing, highest memory-to-logic ratio, and low-power serial transceivers for highest I/O bandwidth
SAN JOSE, Calif., February 5, 2007 – Xilinx, Inc. (NASDAQ: XLNX), the world’s leading supplier of programmable solutions, today announced initial shipments of its 65nm Virtex™-5 SXT field programmable gate arrays (FPGAs) optimized for high-performance digital signal processing (DSP). The SXT platform establishes an industry record for DSP performance delivering 352 GMACs at 550MHz, while consuming 35 percent less dynamic power as compared to previous 90nm generation devices, and is the first DSP-optimized FPGA family to integrate serial transceivers.
The Virtex-5 SXT platform expands the company’s XtremeDSP™ portfolio with three new device options that meet the ultra-high DSP bandwidth and lower system cost requirements of next-generation wireless and video applications. With shipment of the SXT platform, the third of four Virtex-5 FPGA platforms, Xilinx brings the performance, power and cost benefits of the leading-edge 65-nm process node to system developers 12 months in advance of competing solutions.
“The domain-optimized platform strategy pioneered by Xilinx sets the standard for performance, power consumption, cost, and flexibility, all of which are key drivers for helping our customers win in their high-performance DSP markets,” stated Omid Tahernia, vice president and general manager of the Processing Solutions Group at Xilinx. “Our new Virtex-5 SXT platform effectively changes the industry’s traditional view of DSP by providing higher algorithm performance, better power efficiency and lower system cost for a broader range of high-end applications.”
Highest DSP performance with enhanced DSP block and high-speed serial connectivity
The Virtex-5 SXT platform delivers the highest ratio of DSP blocks-to-logic needed for high-performance digital signal processing applications in wireless, such as WIMAX and high-definition video, such as surveillance and broadcast. The enhanced DSP slice (DSP48E) includes a 25x18-bit multiplier, a 48-bit second stage for accumulation and arithmetic operations, and a 48-bit output that can be expanded to 96-bits. The wider data path and output enable increased dynamic range and higher precision as well as optimized support for single precision floating point operations using half the resources consumed by 90-nm FPGAs.
The DSP48E slice also includes integrated cascade routing enabling parallel processing at full 550-MHz speed, delivering an industry-leading 352 GMACs of DSP performance using the 640 DSP48E blocks available in the largest Virtex-5 SXT device. Additional capabilities include an independent C register and an expanded second stage with support for SIMD operations and pattern detection for more efficient DSP implementation.
The SXT platform meets the ever-increasing I/O bandwidth requirements of high-performance DSP applications with up to 16 low-power 3.2 Gbps RocketIO™ serial transceivers that support industry-standard protocols such as CPRI/OBSAI, HD/SDI, Serial RapidIO, PCI Express® and Gigabit Ethernet specifications among others. PCI Express and Gigabit Ethernet standards are supported with built-in protocol blocks and interfaces.
With the industry’s first 65-nm triple-oxide technology, the Virtex-5 SXT platform reduces overall dynamic power consumption by as much as 35 percent and maintains a low static power consumption, which makes it well-suited in defense and public safety applications that require longer battery life, such as handheld software defined radios. Also, the enhanced DSP48E block consumes only 1.4mW/100MHz typical at 38 percent toggle rate, and the Virtex-5 RocketIO transceivers consume as little as 100mW typical at 3.2 Gbps, all of which combine to lower the overall system power and cost.
The Virtex-5 SXT devices range in logic density from 35,000 to 95,000 logic cells and have 192 to 640 dedicated DSP48E slices, providing the highest level of system integration that enables developers to select the right mix of features to optimize overall system cost. These devices also offer the highest memory-to-logic ratio for efficiently implementing memory-intensive functions in video processing and medical imaging with up to 10.3MB of memory offering maximum aggregate bandwidth of 58 Tera-bits/sec. Detailed information on the Virtex-5 SXT family of devices is available at www.xilinx.com/virtex5.
Pricing and Availability
Virtex-5 SXT engineering samples are now shipping for the mid-range SX50T device, with smallest SX35T and largest SX95T devices to follow over the next four months. The SX50T device will list for US$299 in 1,000 unit volumes by the second half of 2008. For even further cost reductions, the Virtex-5 EasyPath™ program offers up to 80 percent cost reduction that will be available at time of volume production.
Customers can immediately begin designing with full support today for Virtex-5 SXT devices in the ISE™ 9.1i design software and new releases of the Xilinx System Generator for DSP and AccelDSP™ tool suites to follow in late February 2007. Virtex-5 SXT devices are also supported through a comprehensive design ecosystem that includes MATLAB, Simulink, C/C++, VHDL, and Verilog design methodologies; a library of optimized DSP algorithms for both basic and application-specific functions; and off-the-shelf design kits.
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.