Lexra offers NetVortex net processor as licensable core
Lexra offers NetVortex net processor as licensable core
By Linley Gwennap, EE Times
June 12, 2000 (9:38 a.m. EST)
SAN JOSE, Calif. Taking a fresh approach to packet processing, Lexra Inc. will announce its NetVortex processor architecture this week at the Embedded Processor Forum.
NetVortex is distinguished from the horde of other network processor units (NPUs) in two ways. First, it executes the standard MIPS instruction set, eliminating the need for complex assembly coding and untested tool chains. Second, it is a licensable soft core, enabling vendors to easily develop custom solutions for their applications.
If Lexra's approach succeeds, it could derail the traditional NPU bandwagon, already crowded with offerings from Intel, IBM, Motorola/C-Port, Lucent/Agere and others.
Those earlier devices all combine several proprietary cores developed from scratch for packet processing. NetVortex instead combines Lexra MIPS-based cores that have been modified for packet processing. The result is similar performance (up to OC-192 routing) without the p rogramming headaches.
Last summer, before the NPU frenzy broke out, a major networking equipment vendor approached Lexra with the idea of building a packet processor. Lexra chief executive officer Charlie Cheng looked at the proposal and said, "You've got to be crazy! That's not a microprocessor it's way too complicated. And besides, no other company would want that thing."
Before discarding the proposal, Cheng mentioned it to one of Lexra's investors. Without waiting for Cheng to finish, the investor said, "Here's a list of companies to talk to."
Within a few weeks, Cheng found six more potential customers and gave the green light to the NetVortex project, then known as Monadnock. In its brief three-year history, Lexra had already developed four versions of its MIPS-compatible RISC core as well as a DSP unit.
However, the company didn't have the resources to develop an NPU from scratch, and the customer wanted something as soon as possible. So the solution was to start with the existing core and tweak it for packet processing.
The biggest performance problem for a general-purpose processor is that analyzing each packet header requires several table look-ups, each of which can stall the CPU for dozens of cycles while it waits for DRAM to respond. Existing NPUs solve this problem using multithreading: instead of stalling, the NPU simply switches to another thread to work on a different packet.
Lexra found it could easily add multithreading to its design, achieving a 3x to 5x speedup on packet processing. The NetVortex CPU, known as the LX8000, supports two to eight threads by simply duplicating the register file for each thread.
A new instruction initiates a load and switches to the next thread, all in a single cycle. The designers also added bit-field insert and extract instructions, extending the standard MIPS bit-processing capabilities to better handle network protocols.
A new two-level branch instruction accelerates the long Case statements often found in multiprotocol router code. These and a few other minor changes deliver a significant improvement on networking benchmarks.
Because NetVortex is available as a soft core, customers can add their own special instructions and even complete coprocessors as needed. For example, a customer might add checksum or hashing functions specific to a particular network protocol. To save space, Lexra stripped out features that aren't needed in a router, such as an FPU and MMU. Instead of a data cache, the LX8000 includes a small dual-ported data memory that's managed by software.
As a result, a four-thread LX-8000 with 16k of instruction cache and 16k of data memory consumes just 3.4 mm2 in TSMC's 0.18-micron process.
Finally, Lexra needed to address the system architecture. NPUs need to move huge amounts of data into and out of the chip at wire speeds. So the company defined the 64-bit Vortex bus, which transfers 3.4 Gbytes/second at the chip's top speed of 427 MHz.
Each LX8000 can connect to up to four internal Vortex buses, delivering a maximum bandwidth of 13.6 Gbytes/s, plenty for even OC-192 routers.
Licensees can choose to run this bus off-chip as well, although probably not much faster than 200 MHz to simplify board design, or they can substitute their own switch-fabric interface. A key benefit of NetVortex is its scalable architecture.
Most NPU vendors to date have released a single configuration that is appropriate for a specific type of device. Additional performance is gained by connecting multiple chips using expensive buses or switch fabrics.
In theory, those vendors could customize their NPU configuration for different applications, but so far they have not. As a homogenous multiprocessor, NetVortex scales easily from single CPU implementations to eight CPUs and beyond.
For example, a licensee cou ld integrate a single LX8000 CPU with an Ethernet interface, an encryption engine and standard peripheral logic to create a processor for a residential gateway or integrated access device.
Along with a DSL or cable modem chip, this processor could provide a network interface with VPN and fire wall support, all for less than $10 for the NetVortex-based chip, according to Lexra.
At the other extreme, the company has mapped out a chip that combines 16 processors using four Vortex buses. This device should be able to handle OC-192 routing, yet it measures only 70 mm2 in a 0.15-micron process.
While other vendors can combine discrete devices to reach this level, Lexra's single-chip solution will be more cost-effective by reducing the number of external chip-to-chip buses as well as overall packaging costs.
Lexra's decision to offer NetVortex as a licensable core contributes to this scalability. Instead of offering a single configuration, Lexra will allow licensees to develop their o wn.
This flexibility makes it easier for licensees to differentiate and add value to their designs. Of course, it also requires licensees to design their own chips, combining NetVortex with other intellectual property as needed. Smaller companies may wish to adopt a prepackaged NPU. Lexra hopes that some licensees will make NetVortex available as an ASSP, serving those customers who don't want to do chip design.
Hard and soft choices
Lexra plans to offer NetVortex as both a hard and soft core. The soft core is expected to reach 250 MHz in a 0.15-micron process. The hard core, which must be optimized for a particular fab, is targeted at 427 MHz. (This odd speed allows the CPU to synchronize with the Sonet clock.)
Lexra has already released the initial NetVortex design to its lead customer and expects the first parts to be in full production by the end of next year.
Lexra will make the NetVortex design database available to other licensees late this year. The standard up-front license fee is $645,000, plus per-chip royalties of $1.00 to $2.50 per core.
Those fees are more expensive than for Lexra's general-purpose cores but still less than for many CPU cores from larger companies. More importantly, no other NPU is available as a licensable core.
Unlike other network processors, some of which don't even have a C compiler available, Lexra's NetVortex is compatible with the vast array of third-party development tools that support the MIPS instruction set.
Programmers must still manually insert the Lexra-specific instructions, such as thread switching and bit extract, but this can be done only in performance-critical inner loops. This compatibility can make a huge difference to network equipment makers, who often create huge software programs to implement complex routing protocols.
Vendors such as C-Port Corp. and Agere Inc. offer high-level programmable tools, but they are in-house tools that are not compatible with third-party efforts. CPU designers love to start with a clean sheet of paper and create intricate hardware designs to squeeze more performance out of a tiny bit of silicon.
But even staying within the bounds of the MIPS instruction set, Lexra crammed a general-purpose CPU into 1.7 mm2. Even if a more specialized design could have cut this size in half, the area saved would hardly be worth the extra programming effort.
Interestingly, both C-Port and Sitera Inc. claim to have based their NPU instruction sets on MIPS, but both veered far enough from that base to make their processors unrecognizable to standard MIPS compilers.
Linley Gwennap is the founder and principal analyst of The Linley Group, a technology analysis firm in Mountain View, Calif.
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