De Man calls for new breed of engineer, tools and methodologies

De Man calls for new breed of engineer, tools and methodologies
By Michael Santarini, EE Times
June 9, 2000 (8:38 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000609S0069

LOS ANGELES—For the IC design business industry to thrive in the post PC era, it will have to formalize system-on-chip (SOC) methodologies, create better architectural-level tools, and cultivate a new class of designer, called an SOC Architect, a keynote speaker said.

Professor Hugo De Man, delivering a Thursday address at the Design Automation Conference here, said the growth of SOC design is creating demand for designers with combined hardware, software and overall system knowledge. "In the 20th century the designer of a chip and the designer of a system were two totally decoupled things," he said. "Chip designers were designing standalone components from ASICs to processors to even wires, but when it comes to systems, it is systems people that are placing wires into an interconnection of different components to build for example a radio on printed circuit board." De Man said those days are over because "thanks to deep submicron technology , engineers can now integrate all the components in hard and soft IP to create a system."

The new SOCs, said De Man, are now part of the new post-PC market—the "Global Network"—in which different components use far more than simply hardware description languages such as Verilog and VHDL. "SOC is never alone. You have to design the environment plus the chips together," said De Man.

Platform proliferation
De Man said there will be several environments or platforms forming the global network and that these environments will need to be highly flexible, power sensitive and accommodate larger amounts of data storage and also be able to more easily transfer that data between one platform to another.

There will be separate platforms for wireless, multimedia, networking and automotive, De Man predicted.

He said at a minimum, SOCs in each of these environments will contain one or more 200 MHz low power RISC processors connected by field programmable busses, as well as have 20 Mbyt es of distributed DRAM and flash memory.

"What we need to do here is discover new methodologies by doing complex designs and then we need to formalize them into methodologies," he said. "If we cannot deliver the languages and tools in time, what we really need to do is raise the education of system on chip designers."

The EDA industry is now getting a handle on the physics gap of timing closure and that tool vendors will need to concentrate on developing effective architectural level design tools, which, according to De Man, are more difficult to create because they address the more ambiguous "architectural gap."

"The architectural gap is really a creative gap requiring knowledge of hardware, software and systems," said De Man.

De Man proposed that the electronics industry invests in a new research effort to create standardized methodologies and develop a curriculum to broadly educate SOC architects in mix of hardware, software and system design.