English
NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Faster verification is the goal at ST
03/05/2007 9:00 AM EST, EE Times
Laurent Ducousso, who manages intellectual-property (IP) verification for STMicroelectronics' Home Entertainment Division, is a man in a hurry. He's in charge of verification for multimillion-gate systems-on-chip (SoCs) that go into consumer products, which have to ship on time. He's succeeding, thanks to a transaction-level SystemC-based approach that both speeds things up and greatly reduces the overall bug count. But debugging and software verification remain challenging. Ducousso recently talked to EE Times editor Richard Goering about ST's verification approach.
Laurent Ducousso, who manages intellectual-property (IP) verification for STMicroelectronics' Home Entertainment Division, is a man in a hurry. He's in charge of verification for multimillion-gate systems-on-chip (SoCs) that go into consumer products, which have to ship on time. He's succeeding, thanks to a transaction-level SystemC-based approach that both speeds things up and greatly reduces the overall bug count. But debugging and software verification remain challenging. Ducousso recently talked to EE Times editor Richard Goering about ST's verification approach.
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