Industry veteran, Michel Courtoy named CEO of Certess
CAMPBELL, Calif. -- March 12, 2007 -- Certess, Inc., a new electronic design automation (EDA) company, today announced plans to tackle the most formidable problem in functional verification: the absence of objective quality assurance in the verification of integrated circuits (ICs) and systems. Most advanced functional verification teams currently use a combination of techniques to gain visibility into the question of verification closure only to continuously fall short of the ability to truly qualify their designs.
With backing from Index Ventures, Certess’ mission is to develop breakthrough technology to perform “functional qualification,” providing verification engineers with the ability to tell if design errors could go undetected and enabling the objective evaluation of the quality of the functional verification, and therefore of the design functionality. Functional qualification will enable design teams to improve their effectiveness and the predictability of their project schedules, which are currently dominated by the verification task
Although verification engineers have dedicated tools and methodologies for verification quality improvement, functional logic errors still remain the largest causes of chip respins. Recognizing the lack of an objective way to measure the quality of chip verification environments, Mark Hampton, Mel Gilmore and Joerg Grosse founded Certess in 2003 and brought in Chairman Jacques Benkoski the following year to guide them. With the technology on the verge of productization, the company hired Michel Courtoy as president and CEO to steer the company’s growth.
“Certess’ founders deep experience with verification tools and methodologies, combined with Michel’s experience and vision, will transform functional verification and finally provide functional qualification to the chip design market” said Jacques Benkoski, chairman of Certess’ board of directors.
Michel Courtoy, who also sits on the board of directors, began his career in design engineering and software engineering with seven years at Intel. He managed product marketing for layout verification software at Cadence Design Systems and held executive positions at Quickturn Design Systems, Osprey Design Systems (which he also cofounded), Aptix Corporation, and Frequency Technology. As vice president of marketing for Silicon Perspective, Courtoy created the market for silicon virtual prototyping and was a key player in the company’s acquisition by Cadence in 2001. Immediately prior to joining Certess, he was vice president at Cadence. Courtoy holds a BSEE from Université Catholique de Louvain, Belgium; an MSEE from University of California, San Diego; and an MBA from Santa Clara University, California.
Jacques Benkoski, chairman of the board and venture executive at US Venture Partners (USVP), served as CEO and president of Monterey Design Systems, which was acquired by Synopsys in 2004. Prior to Monterey, he was in senior management positions at ST Microelectronics, Epic, and Synopsys and served on the EDA Consortium board. He currently serves as executive chairman of Synfora and also advises several of USVP's portfolio companies such as Kilopass, ClearShape, and LightSpeed Logic. Benkoski holds a B.Sc in computer engineering from Technion Israel Institute of Technology, and an MS and PhD in computer engineering from Carnegie Mellon University.
Board member Giuseppe Zocco founded Index Ventures in 1996 and is a general partner. He serves as a director of several public and private companies including Conexant (NASDAQ: CNXT), Telegent Systems, Artimi, and Jaluna. Index Ventures investments in the EDA and IP space include Numerical Technologies (SNPS), Pulsic, Kimotion and Innovative Silicon. Previously, Zocco spent five years as a consultant with McKinsey & Company. Zocco holds a BA in Business Administration from Bocconi University in Milan, an IEP from London Business School and an MBA from the Stanford Graduate School of Business.
Certess, Inc is an electronic design automation (EDA) company focusing on functional qualification for companies that create and integrate complex design blocks or intellectual property (IP). The company’s technology will provide verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs. The company is headquartered in Silicon Valley. For additional information, see www.certess.com.