Language and Tool Independent Verification IP Speeds Development of Power Architecture-Based DesignsPALO ALTO, Calif. -- March 19, 2007
-- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that IBM's next-generation processor local bus (PLB)-4 toolkits have been developed and deployed using Denali's PureSpec(TM) verification intellectual property (IP) platform. The IBM PLB-4 toolkits leverage PureSpec to verify compliance with the latest PLB specification and validate interoperability between the processor cores and integrated bus controllers. These toolkits are now available to developers of Power Architecture(TM)-based designs applying the IBM CoreConnect(TM) on-chip bus technology providing a reliable and comprehensive environment for accelerating design cycle times.
"As the demand increases for interoperable and platform independent Power Architecture solutions, Denali has continually provided invaluable expertise in the toolkit development for the latest PLB specifications," said Michael Paczan, Chairman, Power.org Technical Committee. "IBM's collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
As a member of Power.org and in close collaboration with IBM, Denali has developed verification IP, testbenches, and compliance suites for the PLB-4 specification, which is the most widely-used version of IBM's CoreConnect(TM) on-chip bus specification for Power Architecture-based SoCs. The toolkits are now available as part of Denali's standard verification IP product offerings.
"Our goal is to provide complete, high-quality IP solutions that enable customer success," remarks David Lin, vice president of product marketing at Denali Software. "The collaboration with IBM to deliver comprehensive verification IP products for Power Architecture-based design efforts and our participation in Power.org are perfect examples of how we are working together to enable customer success. The resulting toolkit will help customers to meet aggressive development schedules, while achieving higher-quality designs."About Denali PureSpec
PureSpec verification IP is the most widely used product for verifying functionality, compliance and interoperability of standard interfaces at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the host and one or multiple devices. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design.About Power.org
The Power.org community, formed in 2005, is the collaborative, open organization driving innovation around Power Architecture(TM) technology through alignment of the instruction set architecture, development of standards and specifications, and nurturing of the Power Architecture brand. Power.org's mission is to optimize interoperability, accelerate innovation and drive increased adoption of this leading processor architecture. For more details, visit www.power.org
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND and DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com