GENESYS TESTWARE INTRODUCES FIRST FULL CHIP BEHAVIORAL TEST SYNTHESIS TOOL
Los Angeles, CA, (June 5, 2000) -- Genesys Testware, Inc. today introduced GtshellTM, the first full-chip behavioral test synthesis tool. Gtshell performs full chip BIST resource allocation, architecture generation, interface synthesis and RTL insertion using TestCoreTM IP library. "Leading edge SOC today contain hundreds of memories and several logic cores. Our customers indicated to us that planning, selection, interfacing and insertion of TestCores into such complex SOC is error-prone, and tedious. We developed Gtshell to fulfill this need", said Bejoy G. Oomman, President of Genesys Testware. The IC designer interacts with Gtshell using the industry standard Tool Command Language (Tcl) scripts. Since Gtshell itself is written in Tcl, Gtshell scripts can be executed within any tool containing a Tcl interpreter like Synopsys Design CompilerTM, Cadence Envisio AmbitTM, Synopsys PrimetimeTM, Cadence PearlTM and pubic domain Tclsh. Gtshell has built-in Tcl functions that automate the integration of TestCore with popular memory compilers, synthesis tools, and simulators.
"Designers who combine the proven reliability of our Silicon Ready memory compilers with the capabilities of Gtshell will enjoy the benefits of faster time to volume in leading edge SOC designs", said Mahesh Tirupattur, Vice President of Strategic accounts at Virtual Silicon Technology. "Our Process-PerfectTM memory compilers combined with Gtshell allows our mutual customers to embed advanced memory self-test circuits in their ICs with minimum effort", said Jeff Lewis, marketing manager at Artisan Components. Gtshell can also automatically generate complete synthesis scripts for Synopsys Design Compiler and Cadence Envisio Ambit. Complete simulation scripts can also be generated for most Verilog and VHDL simulators like Verilog-XLTM, Verilog-NCTM, VCSTM, ModelSimTM, VSSTM, and VHDL-NCTM. There is no learning curve for GtshellTM, since Tcl is the scripting language used by most IC designers to interact with synthesis, timing analysis, and simulation tools.
A typical Gtshell script contains four major sections. The first section describes all the memory and logic cores in the design. The name and timing attributes of each port in the memory or logic core is described here. The second section groups memory and logic core instances into clusters that share a BIST circuit. This step can be automatically performed based on estimates of cell area overhead and routing complexity. The third section describes the optional BIST features desired for each BIST circuit. The fourth section specifies information about the design environment like the Hardware Description Language, synthesis tool, simulation tool and the location of synthesis, simulation and TestCore libraries. Finally a write command is used to write all interface files between memory/core models and TestCore models. Configuration header files, top level test case files, synthesis script files and simulation batch files are also written out at this step. Optionally, top level BIST control signals can be propagated up the Register Transfer Level (RTL) design hierarchy and the BIST controllers can then be interfaced to a chip level test controller or directly to chip pins. Gtshell is the only commercial tool that can optimize cell area overhead, routing overhead, and test time for self-test circuitry on a full-chip basis.
Genesys Testware currently provides the TestCore family of products including Memory BistCore for Built-In Self-Test, Diagnosis and Repair (BISTDR) of embedded memories, Boundary ScanCore for board test, core test integration and test pattern reuse and Logic BistCore for BIST of hard cores and on-chip logic to System on Chip (SOC) designers. Each component in TestCore is a library of parameterized, synthesizable, RTL designs. TestCore and Gtshell are licensed as an IC Component Design and as a behavioral test synthesis tool respectively on a site-wide basis to IC design groups using an EDA tool business model. Gtshell is licensed separately from TestCore and is priced starting from $20,000 for a typical design site.
Genesys Testware, Inc. was founded in October 1995 to improve the productivity of designers of large ICs, by providing comprehensive manufacturing test solutions that promote test reuse. Its unique TestCore family of products has been successfully used in many customer designs.
For more information on Genesys Testware or its products, please contact Bejoy G. Oomman, Genesys Testware, 76 Whitney Place, Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498-8734, e-mail: firstname.lastname@example.org, URL: http://www.genesystest.com.