Fluence Technology Announces Test Automation Initiative for Fabless Semiconductor Companies and Design Service Providers
BEAVERTON, Ore.----May 30, 2000-- Fluence Technology Inc.(TM), a leading provider of integrated mixed-signal design and test automation solutions, today announced the Fabless 2000 initiative that will enable fabless semiconductor companies and design service providers to automate the production test development process of electronic devices.
Fluence's Fabless 2000 initiative, based on a new set of software tools, offers an integrated approach to design and test that helps fabless semiconductor companies and design service providers improve productivity and device quality by bringing specified test information to design teams during the design process. Fluence's TestBenchPLUS, available immediately, is the first new product resulting from the Fabless 2000 initiative.
``Fabless semiconductor companies are facing extremely high levels of time-to-market and cost pressures due to rapid growth and short supply of fabrication and test service providers,'' said John Di Girolamo, President/CEO of Fluence Technology. ``When it comes to production test, they are faced with two unattractive options. A design engineer can double as a test engineer, which slows productivity, or an outside test consultant can be hired, which can be hard to find and expensive.''
``To address this situation, we created the Fabless 2000 initiative and a new suite of tools to help design teams compress the physical test cycle by starting it earlier in product development when design errors and test incompatibilities are easier to fix,'' added Di Girolamo.
TestBenchPLUS Eliminates Design and ATE Incompatibilities
The first product under Fluence's Fabless 2000 initiative is the TestBenchPLUS. It allows designers to perform preliminary automatic test equipment (ATE) compatibility analysis at the design simulation phase. This analysis prevents commonly overlooked, yet costly test issues, such as at-speed ATE resource limitation. Oftentimes, design engineers are forced to spin unnecessary cycles revisiting and modifying designs due to ATE resource limitations.
``The earlier in the development cycle that design-to-test incompatibilities are detected, the less costly the design-to-test development phase,'' said Mike Kondrat, vice president of marketing for Fluence. ``Most ATE incompatibility costs can be avoided with TestBenchPLUS. It requires little time investment from the design team, but it yields a tremendous time-to-market advantage by producing designs with 100% tester compatibility.''
Fluence's TestBenchPLUS provides designers with a simple graphical user interface (GUI) that can be activated at the end of each logic simulation and/or automatic test pattern generation (ATPG) run. When working in a Verilog simulation environment, TestBenchPLUS is best used after a Verilog Dump Change (VCD) file is produced. With negligible time in comparison to logic simulations, TestBenchPLUS can help determine whether the event-based VCD file will map onto the cycle-based timing tester. TestBenchPLUS can also recommend design artifact checks and repairs when necessary.
Running TestBenchPLUS at the end of an ATPG run, or when an ATPG/WGL file is received, helps verify whether the fault coverage will hold when the scan data is run at-speed on the tester. Designers can quickly see whether the scan data will compile onto the tester and whether the scan vectors will fit the scan memory on the selected tester.
Additionally, TestBenchPLUS gives designers information about which model of tester is most appropriate for a specified device and whether the contracted foundry or test service provider uses the specified tester. If the designer's contracted foundry does not use the selected model of tester, then TestBenchPLUS can help a designer decide which tester is the next best choice.
Pricing and Availability
Fluence's TestBenchPLUS is available immediately for $8,500. It supports over 90 different ATE models. For ATE-ready designs, an option to generate ATE-specific test timing and patterns is available, and it is priced on a per-project basis. TestBenchPLUS runs on Sun Solaris 2.5 and later.
About Fluence Technology
Fluence Technology is a leading provider of mixed-signal design and test automation software technology and solutions, providing an integrated development environment between ASIC, EDA and ATE suppliers. More than 250 of the world's top electronics companies reduce time-to-market by using Fluence's innovative products, services and support. Fluence headquarters are located in Beaverton, Oregon, with sales offices and distributors throughout the world. Please visit the company's web site at http://www.fluence.com, or contact email@example.com for more information.
Trademarks mentioned in this release are the intellectual property of their respective owners. (c) 2000 Fluence. All rights reserved.
Contact: Fluence Technology Inc.
Mike Kondrat, 503/672-8734
KVO Public Relations
Alison Spoljaric/Andrea Bruce, 503/221-1551