Higher Speed, Lower Power and 2x the Density of 65nm Process
HSINCHU, Taiwan-- April 09, 2007 --Taiwan Semiconductor Manufacturing Company, Ltd. (TSE:2330)(NYSE:TSM) today announced that it would complete 45nm technology qualification and enter production as early as September 2007. The new 45nm process combines the most advanced 193nm immersion photolithography, competitive performance-enhancing silicon strains, and extreme low-k (ELK) inter-metal dielectric material.
TSMC's 45nm low power process (LP) provides twice the density of 65nm with significantly lower power and manufacturing cost per die. End products are expected to achieve 40 percent greater functionality or 40 percent smaller die size, with reduced power consumption. These factors are particularly crucial for system on chip (SoC) designs with an ever-smaller footprint for cell phones, portable media players, PDAs and other handheld devices.
TSMC’s 45nm general purpose and high performance process (GS) provides more than double the density and a greater than 30 percent speed enhancement over the previous generation at similar leakage power, which is especially critical to support applications in PC, networking, and wired communication. The performance boost of 45nm LP and GS has already earned broad acceptance and support among customers, EDA, and IP partners.
“Customers expect both performance and reliability from TSMC, a fact that has guided the development of our 45nm process every step of the way,” said Dr. Rick Tsai, president and CEO of TSMC. “With our 45nm solution ready and production to be started in September, TSMC provides next-generation technology at the earliest possible time.”
TSMC’s 45nm Process
TSMC’s 45nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. With an exceptionally high gate density and high-density 6T SRAM cell, more than 500 million transistors will easily fit into a 70mm2 die area. TSMC’s Low Power (LP) 45nm process is expected to be available first, followed soon zafter by the General Purpose and High Performance (GS) process. In addition, the 45nm logic family includes a low-power triple gate oxide (LPG) option. All three processes offer multiple threshold voltage (Vt) core devices and 1.8V, 2.5V, 3.3V I/O options to meet different product requirements.
CyberShuttle Participation Shows Interest in 45nm
TSMC’s 45nm CyberShuttle is experiencing broad participation, with dozens of customers on board, along with a host of IP vendors supporting the 45 nanometer process. CyberShuttle allows multiple customers to share the costs of a single mask set and prototype wafers on a pilot run. TSMC has successfully delivered functional chips from the industry’s first 45nm Cybershuttle.
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.