Commentary: ESL should drive emulation
(04/13/2007 3:07 PM EDT), EE Times
Conventional wisdom says that when it comes to design, you can either have a design that simulates quickly, but is not accurate. Or, you can have one that is hardware accurate but runs far too slowly for meaningful software debug or architectural performance analysis.
There are hardware acceleration-based techniques that range from off-the-shelf field programmable gate array (FPGA) boards to emulation platforms and multi-million dollar hardware accelerators that can take a detailed hardware implementation and speed up its execution. All require a register transfer level (RTL) representation of the design, which, of course, brings in a new consideration — the time and cost that it takes to develop an RTL model.
While it is relatively inexpensive and quick to develop a functional model, it is time and resource consuming to develop RTL code. These models cannot be developed in a timely fashion to affect design decisions. Further, as software becomes more of a bottleneck to shipping a product, there is a huge need for a platform on which one can begin software testing earlier in the development process.
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process