Shiv Tasker from Bluespec Inc. and Lauro Rizzatti from EVE USA.(04/13/2007 3:07 PM EDT), EE Times
Conventional wisdom says that when it comes to design, you can either have a design that simulates quickly, but is not accurate. Or, you can have one that is hardware accurate but runs far too slowly for meaningful software debug or architectural performance analysis.
There are hardware acceleration-based techniques that range from off-the-shelf field programmable gate array (FPGA) boards to emulation platforms and multi-million dollar hardware accelerators that can take a detailed hardware implementation and speed up its execution. All require a register transfer level (RTL) representation of the design, which, of course, brings in a new consideration — the time and cost that it takes to develop an RTL model.
While it is relatively inexpensive and quick to develop a functional model, it is time and resource consuming to develop RTL code. These models cannot be developed in a timely fashion to affect design decisions. Further, as software becomes more of a bottleneck to shipping a product, there is a huge need for a platform on which one can begin software testing earlier in the development process.
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