PureSpec Verification IP Product Automates Verification of Configuration Registers
PALO ALTO, Calif. -- April 16, 2007 -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the availability of PureSpec(TM) SystemRDL, a verification IP (VIP) product that automates functional verification of configuration registers for system-on-chip (SoC) designs. Configuration registers are used in all semiconductor chips, often numbering in the tens of thousands, to store key data that defines the chip's operation. Denali's PureSpec SystemRDL eliminates the tedious and error-prone process of manually verifying register operations, and enables engineers to automate low-level structural testing, generate functional coverage models, and quickly expose potential errors in the SoC design. A more complete overview of PureSpec SystemRDL technology and applications is provided via webcast at: http://www.denali.com/webcast/purespec_systemrdl
"PureSpec SystemRDL fills an important niche for design and verification engineers," states Sean Smith, chief verification architect at Denali. "We are automating the task of creating verification data structures and functional coverage models for register structures. Even for initial customers, this has translated a tedious 3-6 week effort into a 1-2 days process, which is significant for any chip design effort."
About PureSpec SystemRDL
PureSpec SystemRDL is verification IP (VIP) product designed to automate all aspects of the verification process that relate to control and status registers (CSRs). PureSpec SystemRDL eliminates the tedious and error prone process of describing registers for verification purposes while automatically providing low-level structural testing for registers. The product enables significant productivity gains, by quickly uncovering errors in the chip design and its implementation. The interoperability between PureSpec SystemRDL and other VIP's through a standard callback interface, allows communication with any bus protocol in any of the supported test bench languages, such as: Verilog, VHDL, Specman, Vera, or SystemVerilog. For more information about SystemRDL and to view the webcast, visit: http://www.denali.com/products/purespec_systemrdl/
SystemRDL was specifically designed to describe and implement a wide variety of CSRs. SystemRDL is an object-oriented language with a rich set of features to enable the developers to describe, generate, and verify complex register structures for system-on-chip design. Developers use SystemRDL to automatically generate and synchronize register views for specification, hardware design, software development, verification, and documentation. SystemRDL is also compatible with other SoC development standards such as IP- XACT from The SPIRIT Consortium. This solution has been proven, in numerous large SoC designs, to drastically reduce the development cycle for hardware designers, hardware verification engineers, and software developers. To obtain the SystemRDL language specification, compiler, and other related resources, please visit: http://www.systemrdl.org
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to- market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.