Satin IP Technologies committed to IP Reusability through the launch of VIP Lane, innovative Design-for-Reuse software cockpit
MONTPELLIER, France -- April 18, 2007 – Satin IP Technologies, a privately held startup company located in Montpellier, France, has delivered the first public demonstrations of VIP Lane during the Design And Test Europe conference and exhibition at the Nice Acropolis Convention Center (April 17-19).
VIP Lane is innovative Quality Management software supporting design engineers and project managers in their efforts to make Design-for-Reuse a daily reality.
By complementing and inter-operating with the Electronic Design Automation and Product Lifecycle Management tools that typically constitute semiconductor design flows, VIP Lane is a powerful and flexible implementation channel for the Design-for-Reuse processes which semiconductor companies usually have in place. Running as a web server application, VIP Lane tracks and captures all parameters and objects affecting IP quality, from multiple sources throughout the IP design and integration lifecycle. Taking advantage of its patented Design Quality Abstraction Layer, VIP Lane offers “checklist-driven” design assistance in the most critical areas of design reuse: specifications, coding, implementation, verification and support of SoC integration.
The CEO of Satin IP Technologies, Michel Tabusse explains: "IP quality results from a number of engineering practices throughout the block life cycle, and requires careful daily management rather than subjective scoring a posteriori. Large semiconductor companies, as well as IP vendors, cannot meet their objectives merely by using the most up-to-date EDA and PLM software. Most companies have defined best design-for-reuse practices internally and see a need to get those practices adopted throughout the design teams without incurring additional productivity costs. With VIP Lane, we provide the opportunity to do exactly that.” VIP Lane has already delivered value to several IP design projects at the Laboratoire d’Informatique, Robotique et Microélectronique de Montpellier (LIRMM, CNRS) and at Netheos, a company specialized in encryption solutions.
"Getting into the IP market is no easy decision for a company like us selling turnkey security solutions to final customers,” said Xavier Facélina, general manager at Netheos, “the Designfor- Reuse expertise accessible from VIP Lane was instrumental to our decision to market encryption solutions in the form of Intellectual Property blocks.”
“With VIP Lane as a key element of our IP qualification process, we identified and launched corrective actions on our Network Processor Unit that may otherwise have been ignored,” said Professor Lionel Torres, in charge of the System Level Architecture program at LIRMM. “We will standardize on VIP Lane for qualifying the reusability of our future IP blocks.”
About Satin IP Technologies
Satin IP Technologies is a privately held company with offices in Montpellier, France. The company was founded in 2006 by EDA professionals (Electronic Design Automation) with decades of experience in the development and sales of implementation and verification IP. Satin IP Technologies develops and licenses VIP Lane, Quality Management software targeted to designers of reusable Semiconductor IP blocks.
The company expects VIP Lane to make “Design for Reuse” and “Core-Based Design” easier and more productive activities for IP and SoC designers.
Visit Satin IP Technologies online at http://www.satin-ip.com.
|
Related News
- Intento Enters EDA Market with Software that Accelerates Analog and Mixed-Signal Design, Enables IP Re-Use Through Technology Migration
- Magillem promotes IP Reuse, interoperability through IEEE 1685 and launches its IP-XACT Checkers Suite Software and Compliance Lab
- Cost pressures spotlight design-for-reuse
- Secafy selects Siemens' EDA tools for innovative hardware security development
- Siemens introduces Innovator3D IC - a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |