A panel discusses 65-nm mixed-signal design

Anne-Francoise Pele, EE Times:
(04/20/2007 5:52 AM EDT)

NICE, France -- The demand for analog/mixed-signal intellectual property (IP) blocks has never been greater, especially at the 65-nm process node and below. At a panel discussion at the DATE conference this week in Nice, France, speakers called for a new breed of analog designers who would be able to face the power dissipation constraints, due to the increased leakage, device variability and model accuracy, and new design methodologies and tools for enhanced reliability.

"Today, at the 90-nm process node, we are able to integrate multiple cores on systems-on-chip (SoCs), and the percentage of SoCs with mixed-signal content is growing from about 10 percent in 1998 to about 70 to 80 percent in 2006," declared Georges Gielen, a professor at Katholieke Universiteit in Leuven (Belgium) and moderator of the panel.

The bad message, he continued, is that the productivity of analog designers is quite low. It is estimated at about 1 device per hour compared to thousands of devices per hour on the digital side. Moving to the 65-nm process node and below, he identified new obstacles. The supply chain is dropping. The variability is becoming a problem in analog circuits. And, as we integrate different blocks in the circuit, interferences limit its performance.

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