SAN MATEO, Calif. The EDA industry's two largest vendors have joined forces with major industry standards groups to move tool interoperability to the next level, as Cadence Design Systems Inc. announced that it has licensed its Library Exchange Format (LEF) and Design Exchange Format (DEF) to Synopsys Inc.
In addition, the EDA Consortium announced that Synopsys and Cadence have completed the EDASpine tool interoperability initiative and have opened the doors for any and all EDA vendors.
Cadence also hinted that the Silicon Integration Initiative (Si2), an industry standards group, will release its Interoperability Model which includes LEF and DEF at the Design Automation Conference (DAC) in Los Angeles on June 9. Meanwhile, Cadence is expected to take the wraps off its common tool database, code named "Genesis," at DAC.
Synopsys (Mountain View, Calif.) and the rest of the EDA industry had been waiting since 1998 for Cadence to release LEF and DEF, which are de facto standards for transferring data to physical design tools.
At the 1998 Design Automation Conference, Cadence's president and chief executive officer at the time, Joseph Costello, announced that Cadence would release LEF and DEF. But not until this week, and after much industry prodding, did Cadence license its formats to Synopsys, which over the last year has jumped into the physical design space to become a more direct competitor to Cadence.
At the upcoming DAC, Si2 is expected to announce the release of LEF and DEF to the rest of the industry.
Sue Lubais, marketing director for Cadence's new database, said the company will unveil its common database at DAC that closely links Cadence tools along with third-party tools. Lubais said the database is similar to the Milkyway common database of Avanti Corp., but has "better performance and several A PIs to link to third-party tools."
Karen Bartleson, director of interoperability at Synopsys, said her company will use the LEF and DEF formats for its Physical Compiler and Physical Synthesis tools, and in Spine, an effort of the EDA Consortium to further the interoperability of EDA tools.
"We are very excited that Cadence has licensed the formats to us," Bartleson said. "It shows that we are maturing as an industry."
Separately, the EDA Consortium announced that the EDASpine tools from Synopsys and Cadence are now available in the Synopsys Secure User Research Facility (Surf), in Mountain View, Calif.
Pat Dutrow, program director for the Cadence Connections Program, said the Spine program will allow all interested parties to test interoperability with Synopsys' widely used Design Compiler synthesis tool and with Cadence's Silicon Ensemble place and route suite.
Dutrow said that Spine members have to sign a restriction clause that says among other things that t hey will only use the Surf facilities to check interoperability, and will not use it for benchmarking or performance testing. "It is for companies who want to test their products within a commonly used synthesis to place and route flow," said Dutrow. "They can test and document the valid data exchange points between their tools and EDASpine."
The integration of Simplex Solution's SoC verification tools and Ultima Interconnect Technologies' interconnect analysis tools into the EDASpine will be showcased at DAC at the EDA Standards Booth 3711.
Search words: LEF, Cadence, Synopsys