Synopsys and Tensilica Partner to Provide New Cycle-Accurate Model Generation Platform

MOUNTAIN VIEW, Calif.----May 24, 2000-- Synopsys, Inc. (Nasdaq:SNPS), and Tensilica Inc. have jointly developed an automatic model generation platform for fast hardware/software co-verification models of system on a chip (SoC) designs.

Tensilica expanded its virtual prototyping environment to include support for the Synopsys Eaglei® hardware/software co-verification tools and required models that can be generated in less than one hour from a high-level processor configuration description. Now, system designers can choose area, speed, power, and code density tradeoffs prior to hardware synthesis.

The automatic model generation platform quickly produces cycle-accurate co-verification models of a customer-configured Xtensa(TM) 32-bit configurable processor. The combination of the uniquely configured model of Xtensa with Synopsys Eaglei provides a highly efficient environment that allows rapid verification of software algorithms early in the process and permits fast exploration of tradeoffs before committing to silicon. The result is smaller, higher-performance, lower-power designs.

``Support for hardware and software co-verification is critical in achieving time to market on Xtensa-based designs,'' said Chris Rowen, president and chief executive officer for Tensilica. ``High-performance products like Synopsys Eaglei allow designers the ability to eliminate unnecessary and costly re-spins on their SoC designs prior to tape-out. With Xtensa, there are no compromises between the optimality of application-specific processor and the convenience of world-class third-party tools.''

Synopsys Eaglei has been successfully proven to reduce design cycle time on very complex, multimillion-gate, multiple processor designs. By taking advantage of the virtual prototype environment with Synopsys Eaglei, customers are able to rapidly meet their SoC design requirements.

``Synopsys recognizes Tensilica as a leading provider of configurable microprocessor cores,'' said Geoff Bunza, vice president and general manager of the large systems technology group for Synopsys. ``By offering a high-performance hardware and software co-verification solution with Tensilica and Synopsys Eaglei, we are giving our mutual customers the ability to gain new levels of design productivity.''

About the Technology

By extending the processor with unique application-specific instructions, Xtensa allows designers to gain factors of 2-10X in software performance while eliminating ``hardwired'' custom logic blocks that are difficult to design, integrate and test. By supporting these custom functions in the instruction set, much more of the system can be modeled at high speed and with high visibility using the Synopsys Eaglei hardware/software co-verification tool and the Xtensa processor model. By synchronizing the system hardware and software development throughout the design process with Synopsys Eaglei, users have reported improvements on the quality of results and design cycle reductions of over 30 percent. Historically, interfaces between hardware and software have not been tested together for consistency and accuracy until the system prototype phase. This is when errors first become apparent, even if they have existed since early in the design. The Synopsys Eaglei environment bridges the hardware design and software development processes, making it possible to simultaneously verify the interactions of both parts of the process.

The entire Tensilica tool chain, including support for Synopsys Eaglei, is downloadable by the customer directly from the Tensilica Web site. Licenses for Synopsys Eaglei tools are available from Synopsys.

Tensilica's Xtensa Configurable Microprocessor Core

Xtensa allows embedded system designers to rapidly build differentiated, optimized and synthesizable processor cores for use in ASIC/ASSP-based products. Designers can use the Xtensa processor generator to configure a processor; to concurrently create a complete GNU-based software development environment (compiler, assembler, linker, profiler, debugger); to create an instruction-set-simulator; and to produce a configurable interface to popular Real Time Operating Systems and to add designer-defined instructions uniquely developed for the target design. The instruction-set simulator and bus functional model can be used by the Synopsys Eaglei co-verification environment to model the new processor configuration along with any new designer-defined instructions. The Xtensa processor features an industry-leading, code-efficient instruction set architecture, a typical clock frequency of 320 MHz, which occupies less than 1.0-square mm and dissipates less than 0.4-mW/MHz in 0.18 mm technology.

The Synopsys Eaglei Verification Solution

The Synopsys Eaglei hardware/software co-verification solution is part of a powerful suite of Synopsys system-level design and verification products and services that includes: VCS(TM), the industry's fastest Verilog simulator; Scirocco(TM) for high-performance VHDL simulation; a comprehensive range of proven Logic Modeling® IP models for simulation; VERA(TM) testbench automation and analysis products; PrimeTime®, the industry's leading static timing analysis and sign-off tool; and Formality®, a formal verification tool for equivalency checking of multimillion-gate designs. For more information, contact your local Synopsys representative, e-mail verify@synopsys.com, or, in North America, phone 800/346-6335.

About Tensilica

Tensilica(TM) Inc. was founded in July 1997 to address the fast-growing market for application-specific microprocessor cores and software development tools in high-volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, SoC designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The company has over 80 engineers engaged in research, development, and customer support from its offices in Santa Clara, Calif.; Waltham, Mass.; Princeton, N.J.; Houston; Reading, United Kingdom; and Yokohama, Japan.

Tensilica is headquartered in Santa Clara, Calif. 95054 at 3255-6 Scott Boulevard, and can be reached at 408/986-8000 or via www.tensilica.com on the World Wide Web.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys, Logic Modeling, Synopsys Eaglei, PrimeTime and Formality are registered trademarks and VCS, Scirocco and VERA are trademarks of Synopsys, Inc. Tensilica and Xtensa are trademarks of Tensilica Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Contact:
     Synopsys, Inc.
     Brenda Westcott, 650/584-1331
     brenda@synopsys.com
       or
     Tensilica(TM) Inc.
     Rey Archide, 408/327-7315
     archide@tensilica.com
       or
     KVO Public Relations
     LeAnne Frank, 503/221-7403
     leanne_frank@kvo.com
       or
     The Leapfrog Group
     Kim Alfaro, 415/563-4769
     kimpr@holonet.net