Bus Fabric Components, Transactor Libraries Accelerate and Unify System Modeling, Implementation and Verification
Waltham, Mass. – May 7, 2007 – Bluespec™ Inc. today added system-level building blocks to its AzureIP™ Foundation Library, a family of pre-packaged and verified intellectual property (IP) and design reuse capabilities to accelerate electronic system level (ESL) design and verification.
The new blocks include ARM® AMBA® AXI® and AHB and Open Core Protocol (OCP)-IP interface bus component libraries comprising parameterized bus structures, bus interface transactors and data type libraries.
“Bus fabric complexity and concurrency overstress existing design tools and dominate system-on-chip development schedules,” remarks Charlie Hauck, vice president engineering of Bluespec. “With highly-parameterized, transaction-level designer viewpoints, Bluespec’s AzureIP bus fabric libraries enable rapid, true design exploration with an automated path to high-quality implementation.”
Falling between low-level IP components like adders and multipliers and large IP blocks like Ethernet, PCI, H.264 and processors, these blocks fill a void in the middle of the IP space, an area used most often by internal design teams, but inadequately addressed with current IP due to the level of customization required for each application.
Bus Fabric Libraries for AMBA AXI, AMBA AHB and OCP
The Bluespec AzureIP bus fabric libraries enable modelers and designers to quickly and correctly create and connect to bus fabric interfaces and channels that are compliant with industry-standard bus and communication protocols. The initial release supports three industry standard bus protocols:
AMBA – AXI
AMBA – AHB
Bus Interactions at the Transaction Level
At the heart of Bluespec's bus fabric IP offering is a unique Transaction Level Modeling (TLM2) bus payload data structure and protocol. This generic representation supports multiple bus protocols and is based on OSCI’s TLM 2.0 draft specification. Use of the TLM2 representation allows customers to work with bus interactions on a transaction level, whether for high-level modeling or efficient hardware implementation. The details of each bus-specific signaling protocol are encapsulated within the library building blocks, eliminating the need to be re-designed and re-verified each time a design includes channels or interfaces based on that protocol.
For each supported bus protocol, the associated AzureIP package includes the following components:
Master Transactor - Converts a stream of TLM2 operation descriptors, communicated through transaction level GET/PUT interfaces, into a sequence of protocol-specific bus operations.
Slave Transactor - Converts a sequence of protocol-specific bus operations into a stream of TLM2 operation descriptors, communicated through transaction level GET/PUT interfaces.
Bus Fabric Constructor - Module constructor that, given a set of master and slave interfaces, creates the complete bus fabric and any associated arbiters as required.
The unique capabilities of Bluespec's patented technology allow customers using these packages to achieve levels of design reuse unavailable using other technologies. Since the AzureIP package components are implemented natively in Bluespec source, they do not represent fixed modules with a few, pre-selected degrees of parameterization. Instead, each package component represents a design template, which is automatically transformed by the Bluespec compiler into a specific, highly efficient instantiation, parameterized and optimized to the specific application context of each use. Unused capabilities are automatically removed, saving power and area as compared to the results that can be achieved using more traditional hardware IP.
As the TLM2 structure is common to different bus structures, entire designs can be completed and verified independent of the specific bus protocol selected for each interface or communication channel. This allows a single design to be used in multiple applications, each time using a different set of selected bus protocols. This flexibility also allows designers to postpone decisions regarding which specific protocols to use until very late in the design cycle.
AzureIP Foundation Libraries
Bluespec, developer of the only ESL synthesis for control logic and complex datapaths in chip design, has developed these libraries to offer ESL designers flexibility, along with an ability to modify and synthesize their designs. The AzureIP Foundation Library, first introduced earlier this year, is a path to faster time to market, rapid design composition, including customization and reuse, increased quality and decreased verification costs.
Built at the transaction level for quick simulation, blocks can be automatically compiled to efficient, detailed register transfer level (RTL) code. Blocks can be used at any level of abstraction, from abstract, system-level modeling to a more detailed ESL implementation. Parameterized building blocks deliver plug-and-play customization.
Bluespec’s entire product line will be demonstrated in Booth #6963 during the 44th Design Automation Conference (DAC) June 4-8 at the San Diego Convention Center in San Diego, Calif.
Pricing and Availability
The AzureIP Foundation Libraries are included as part of Bluespec’s ESL software. Design services are available to even further accelerate system modeling and implementation.
Contact George Harper, Bluespec’s vice president of marketing, for more details. He can be reached at (781) 250-2200.
Bluespec Inc. manufactures industry standards-based Electronic Design Automation (EDA) toolsets that significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolsets, including the only ESL synthesis tools focused on control and complex datapaths, allow ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling (781) 250-2200.