Functional Qualification Provides the Objective Assessment of Verification Quality CAMPBELL, Calif. -- May 7, 2007
-- Certess, Inc. today launched Certitude, the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks. Certitude certifies that if a semiconductor chip design had a bug, it would be found. It tackles the most formidable problem in functional verification: the absence of objective quality assurance in SoCs and IP blocks.
"Certitude enables companies to optimize their verification resources and budget," said Mark Hampton, CTO of Certess. "We've worked with several major semiconductor and systems companies over the past three years to ensure that Certitude delivers on the promise of functional qualification, and it has proven itself every time. It qualifies the whole verification process and removes the uncertainty that accompanies many design projects."
Certitude addresses two of the most critical problems associated with the design of semiconductors: first, that the functional verification process consumes more resources than the design process; and second, despite having a set of dedicated tools and methodologies that automate parts of the process and improve verification quality, companies find that functional logic errors are still the largest cause of silicon re-spins.
Certess' patent pending technology, which has performed the functional qualification of numerous projects at large semiconductor and systems manufacturers, objectively analyzes, measures and enables the improvement of functional verification environments for complex designs. Certess has combined a technology known as mutation analysis with decades of experience in functional verification to create Certitude. Mutation analysis is based on the concept of introducing atomic changes called mutations in the HDL description of the design; if the change is not detected, it exposes a weakness in the design's verification environment. A number of innovative proprietary algorithms were developed by Certess to enable the exploitation of mutation analysis for the functional qualification of industrial systems.
"Certess first got ST's attention a couple of years ago when they claimed -- and then went on to prove -- that their functional qualification technology could find critical verification environment weaknesses that no other tool could find," said Jean-Marc Chateau, group vice president at STMicroelectronics, IP & Design. "ST now uses the Certess technology company-wide to provide an objective measure of quality. We are now able to measure with confidence the efficiency of the functional verification of the IP blocks integrated in our SoCs and deliver chips with higher quality to our customers."
According to Certess CEO Michel Courtoy, Certitude is already deployed by more than 50 design teams in integrated device manufacturers, fabless semiconductor companies, and system manufacturers throughout the world.
Certitude's functional qualification has been used by design teams with two distinct goals. The first one is the improvement of the quality of the functional verification for IP blocks and SoC designs. In this use model, Certitude assists the user to trace back from the undetected mutations to identify the missing or erroneous elements in the functional verification environment. These areas in the verification environment could hide a bug in the design that needs to be fixed before the design quality can be ensured and the design is ready for production release. The second goal is to objectively measure the quality of the verification. In this use model, Certitude provides an objective and quantitative measurement of the quality of the design and its associated verification environment.
"There is a large hole in most ASIC verification methodologies today, and it is the ability to measure the completeness of the verification environment. Certitude fills this hole, enabling us to discover where our checkers are missing or incomplete," said Carey Kloss, verification manager at Aquantia, a leading developer of 10GBASE-T. Kloss has been recognized for pioneering leading-edge verification methodologies over his years at Cisco Systems and other leading networking companies. Compatibility and Availability
Certitude is complementary to existing EDA products and does not require any modification of the customer methodology or toolset. It currently supports Verilog and VHDL; SystemVerilog will be available in Q4'2007. It is tightly integrated with all industry-standard simulators and is fully compatible with verification methodologies such as random-based stimulus generation and PSL assertions. Certitude can be deployed in under a week in most existing environments. Certitude produces a browsable HTML report that shows the results of each analysis, and has a TCL shell interface. The product is available immediately. About Certess
Certess, Inc. is the only electronic design automation company providing functional qualification products for companies that create and integrate complex design blocks or intellectual property (IP). The company's technology provides design and verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs and ensure high quality designs. The company is headquartered in Campbell, CA. For additional information, see www.certess.com