Silicon Interfaces announces the release of its new RapidIO Physical Layer Interface OpenVera Verification IP
Silicon Interfaces’ RapidIO Physical Layer Interface OpenVera Verification IP is a fully documented, off the shelf component for the verification of the RapidIO Physical Layer Interface Controller. RapidIO is a Packet-switched Interconnect primarily intended for an Intra-system Interface for chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels.
OpenVera Verification is a comprehensive test bench automation solution for module, block and full system verification. Open Vera is an intuitive, high-level, object-oriented programming language developed specifically to meet the unique requirements of Functional Verification. OpenVera enables generation of high coverage, constraint-driven random stimulus generation. With OpenVera, it is easy to quickly model the target environment at a high level of abstraction while automatically generating constrained random stimulus.
Constraint driven random stimulus in Open Vera enables the detection of a wide range of bugs including functional and corner cases. Along with it, Open Vera supports Multilanguage Verification namely all HDLs including VHDL, Verilog and SystemC.
Product Highlights:
- Full Randomized Flow Control of the Packets.
- Input number of Packets from the Command Line.
- Single User entry driven root-level Seed.
- Randomized selection of various Packet generation tasks.
- Optional Inclusion of OpenVera Assertions Engine.
- Score Board for User / Link Interface.
- Score Board for Fabric Interface.
- Optional Randomized Injection of Control Symbols on the Fabric Interface.
- Full Automation in conjunction with constraint-driven randomization.
- Loop-Back mechanism for the Packets transmitted by the DUT to the Fabric.
- Preliminary DUT Health Check-up, to check its heart beat prior to transmission.
- Randomizing pulsing of TIME-OF-DAY Control Symbol from User / Link
- Interface.
- Randomized Byte Enable for Data on User / Link Interface.
- Supported with ‘DEFINES’ file for Top-level OpenVera Testbench, User / Link and Fabric end tasks.
- Randomized Inter-packet gap generation.
- This product comes along with highly comprehensive documentation.
Availability
The RapidIO Physical Layer Interface OpenVera VIP is available now.
About Silicon Interfaces
Silicon Interfaces has experience in verification solutions and developing IPs for Fabric Channel Interconnect, Telecom and Networking domains, including Bluetooth Baseband, Gigabit Ethernet MAC, SONET Framer STS-1/3, 1394, USB2 Function Controller, USB On-The-Go, USB 2.0 OVA Checker AIP, Infiniband, 8530, 8051, 7990, UART, Rapid IO , 802.11 a/b/g MAC, PCI-Express, 10 Giga and SONET STS Framer –12. These IP have had considerable maturity based on certification, targets to various FPGA devices and ASIC libraries, silicon area optimization, silicon prototyping and testing. Also available are OVA VIPs and an extensive driver development program which enables the company to offer a packaged solution to the customer. For more information please visit www.siliconcores.com
|
Silicon Interfaces Hot IP
Related News
- Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP
- Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC
- Silicon Interfaces announces its OVM Based IEEE 1394 Link Layer Controller Verification IP
- Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM)
- Silicon Interfaces announces the release of its new Verification Intellectual Property Gigabit Ethernet MAC OVA Checker VIP
Breaking News
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- TSMC Celebrates 30th North America Technology Symposium with Innovations Powering AI with Silicon Leadership
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |