Once characterized by long development and product life cycles, the communications infrastructure is now in a state of near constant flux, thanks to the accelerating pace of advances in technology and more sophisticated consumer expectations.
"The universe of communications is changing so rapidly, OEMs not only have to get out [into the market] quickly, but they have to future-proof their equipment," said Bruce Kleinman, senior director of marketing at Chameleon Systems Inc., a newly funded chip supplier in Sunnyvale, Calif.
As its name suggests, Chameleon offers a technology that lets OEMs change a system's design at a moment's notice, without interrupting its operation, to accommodate standards updates, new protocols, or new algorithms.
The ability to deliver instantaneous reconfigurability has been held up as the communications market's Holy Grail. For example, if a next-generation cellular base station could at any point in time realloca te its processing resources to handle varying traffic characteristics, the savings in system hardware and maintenance costs would be enormous and the base station's life cycle would be extended, Kleinman said.
"An OEM could effectively create, on the fly, hundreds of different chips," said Chuck Fox, Chameleon's president and chief executive. "This could have a profound impact in this decade."
Though a number of reconfigurable computing approaches have been tried -- and many more are in development -- none has yet delivered the right combination of computing performance and flexibility, analysts said.
Chameleon today will try to change that when it unveils its first product -- a chip intended to be a platform on which customers can develop high-speed reconfigurable communications processors. Its generic design betrays a powerful mix of processing elements, programmability, and a fast datapipe that together enable code modifications in microseconds without compromising system performance.
Dubb ed the CS2000, the chip combines the best features of FPGAs, ASICs, and DSPs, while avoiding the pitfalls of each, said Fox.
"When a DSP runs out of gas, people will go to an ASIC or an FPGA, but then they're back to stitching things together to make more ALUs [arithmetic logic units]," Fox said. But while the ASIC design cycle is too long for most communications infrastructure designs, FPGAs are not powerful enough to compute complex algorithms, he said.
Chameleon's platform approach "shifts the focus from verifying transistors to creating algorithms -- and doing it fast," Fox said.
Chameleon will target its CS2000 reconfigurable pro- cessor at applications requiring large banks of DSPs operating in parallel. Where a typical base station or central-office application might require 100 to 200 DSPs, Chameleon says it can reduce that number to eight or 10 chips.
Chameleon is "plowing new ground" by offering a chip that performs high-end DSP functions that, until now, have required specialized c ustom silicon, said analyst Will Strauss of Forward Concepts Co., Tempe, Ariz. "The CS2000 will get a lot of interest in hot new DSP markets like 3G-wireless base stations," Strauss said.
At the heart of Cha- meleon's architecture is a 32-bit reconfigurable processing fabric containing an array of 12 programmable tiles, each featuring a bank of 32-bit data-path units, single-cycle multipliers, local-store memories, and a control logic unit. The fabric is connected to an embedded-processor system through an on-chip 128-bit bus that provides 2-Gbyte/s I/O bandwidth.
The embedded-processor system is composed of a 32-bit reconfigurable processor core licensed from ARC Cores Ltd., a 32-bit PCI bus and controller, a 64-bit memory bus and controller, and configuration and DMA subsystems. Surrounding the device are 160 programmable I/O pins.
Instantaneous reconfigurability is enabled by dual configuration planes that Chameleon has dubbed eConfigurable technology. A new configuration can be loaded into th e background plane in a single clock edge without disrupting the operation, according to Kleinman. "This provides not only better performance, but lower power consumption and lower cost because it allows more channels per chip," he said.
The initial product, CS2112, produced on a fairly conservative 0.25-micron process, delivers a claimed 24 billion 16-bit operations/s, 3 billion 16-bit multiply accumulates, 50 channels of cdma2000 Chip Rate Processing, and 16 channels of UMTS Chip Rate Processing.
The Chameleon Systems Integrated Development Environment (C-SIDE) provides a tool kit for designing, debugging, and verifying reconfigurable communications processor designs in C and HDL. It includes a GNU C compiler for the 32-bit processor, an optimized HDL synthesizer for the reconfigurable processing fabric, and a full-chip simulator.
Chameleon's eConfigurable Basic I/O Services (eBIOS) provides a seamless interface between the embedded processor system and the fabric, the company said.
The CS2 112 is slated to sample in the third quarter. Pricing will start at $295 in 100s. High-volume pricing by the second half of 2001 is expected to be less than $1 per cdma2000 Chip Rate Processing channel. The C-SIDE development tools will ship in the third quarter, priced at $25,000 per seat.