Newark, Calif. -- May 29th, 2007 -- ASIC IP, a leading provider of semiconductor intellectual property (IP) and design integration solutions, today announced the availability of their Serial ATA (SATA) Controller Core interface that is efficient and configurable to various applications. ASIC IP SATA Controller Core provides flexibility and ease in integration to customized software and both Host and Device applications. The SATA Core supports both Gen I and Gen II speeds.
Some key features
The ASIC IP SATA application supports both PIO and DMA modes. It has a SAPIS Version 0.9 Compliant PHY Interface, configurable Transmit and Receive FIFOs, and operates up to 100MHz on an Application Clock. It offers an easy to use DMA interface with a DMA hold-off capability, elasticity buffer implemented in Link Layer simple VSIA’s PVCI interfaces on the application side, and supports both Partial and Slumber Power Management modes.
The Verilog based modular design allows it to decode all the received FISs, except DMA FISs and support Set Device Bits and BIST Activate FISs. The SATA also has dual-scramblers which allow for repeated primitive suppression.
“This new ASIC IP SATA Core interface allows our customers to use a better design at a lower cost with a faster time-to-market and excellent global support," said Jitu Choudhury, Founder of ASIC IP.
Availability, Pricing and Support
ASIC IP’s enhanced Serial ATA Controller Core is available now for a free evaluation. Currently ASIC IP is offering the GEN-I SATA which can easily be upgraded to the GEN-II SATA. Pricing is based on ASIC IP’s technology licensing model. As with all ASIC IP products, they offer customized design and integration with excellent 24/7 customer support.
About ASIC IP
ASIC IP is a Semiconductor Intellectual Property (SIP) company. Its founder, Jitu Choudhury, brings his educational background with over ten years of experience in EDA, IP core and design services to ASIC IP. ASIC IP offers solutions in IPs, design integration, place and route, analog design, design verification, ASIC IP’s sales and marketing is based in Silicon Valley, California.
ASIC IP is dedicated to providing the system on chip (SoC) designers, the highest quality silicon proven connectivity IP controllers, physical (PHY) layers, microprocessors, power management solutions, and design integration solutions from worldwide suppliers.
For additional information, visit www.asicip.com