CEVA-TeakLite-III extends the capabilities and more than doubles the performance of popular CEVA-TeakLite core targeting emerging consumer and wireless applications
SAN JOSE, Calif. -- May 31, 2007 -- CEVA, Inc. (Nasdaq: CEVA; LSE: CVA), a leading licensor of innovative IP platform solutions and DSP cores for wireless, consumer and multimedia applications, today announced the CEVA-TeakLite-III(TM), a third-generation DSP architecture based on the broadly adopted TeakLite family of DSP cores. This feature-rich native 32-bit architecture is backward compatible with previous versions of CEVA-TeakLite(TM) cores and delivers higher performance and lower power for demanding applications such as 3G cellular handsets, High Definition (HD) audio, Voice-over-IP (VoIP) and portable audio devices.
For the first time, a DSP compatible with the CEVA-TeakLite architecture delivers native 32-bit processing, which includes a 32 x 32 MAC unit to provide efficient support of advanced audio standards such as Dolby Digital Plus 7.1, Dolby TrueHD, DTS-HD and more. The architecture also features a 10-stage pipeline, enabling the core to reach operating speeds of up to 425MHz in a 65nm process (worst-case conditions and process). Compared to CEVA-TeakLite, initial performance estimates show it to be up to 4 times faster on basic operations and 2 times better on most popular audio codecs.
"High-volume applications such as HD audio and multi-mode handsets require a DSP engine offering substantial performance, at low power consumption and smallest die size," said Gideon Wertheizer, CEO of CEVA. "Both new customers and the large install base of licensees with CEVA-TeakLite legacy software investment will benefit from the performance and features that CEVA-TeakLite-III offers to extend the capabilities and market reach of their next generation products."
CEVA-TeakLite-III builds on the architecture of CEVA-TeakLite-II(TM), CEVA-TeakLite, and CEVA-Oak, the most established and successful licensable DSP architecture to date. The CEVA-TeakLite family has been licensed to over 50 partners worldwide and has shipped in over 750 million devices. CEVA- TeakLite-III is fully compatible to CEVA-TeakLite and CEVA-Oak architectures, allowing its users to leverage both existing applications and the large software installed base already available from CEVA and the CEVAnet(TM) third-party development community.
The flexible CEVA-TeakLite-III architecture is available in various configurations, each specifically tailored for particular applications and system architectures. CEVA-TL3210 and CEVA-TL3214 are two specific configurations of the architecture, available for licensing today. CEVA-TL3210 includes a mix of tightly coupled memories and direct mapped caches, and allows easy SoC integration using AHB bus protocols. CEVA-TL3214 targets cost sensitive SoCs based on a TeakLite-compatible X/Y data structure and minimizes SoC integration investments. An additional configuration, the CEVA-TL3211, includes an advanced 2-level cached memory subsystem equipped with a memory protection unit and AXI system interfaces. This configuration targets single-core embedded applications and will be available for licensing in early 2008.
Targeting next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption. For example, a 7.1 channel Dolby Digital Plus decoder would consume only 15% of the core's available MHz at a 90nm process, compared to 47% for its predecessor, the CEVA-TeakLite.
3G multimode and portable audio applications are enhanced through dual 16-bit multipliers, a built-in Viterbi accelerator and a set of SIMD and parallel instructions. By utilizing a 10-stage pipeline, the CEVA-TeakLite-III runs at 350MHz in a 90nm G process, and up to 425MHz in a 65nm G process, using the worst-case corner.
The new CEVA-TeakLite-III DSP architecture embeds CEVA's patented CEVA-Quark(TM) instruction set, a comprehensive stand-alone 16-bit ISA that allows customers to develop complete applications for cost-sensitive markets. Moreover, customers can seamlessly mix CEVA-Quark instructions with more advanced instructions without the need for mode switching. This enables better code density for CEVA-TeakLite-III based designs and requires less memory, die size and power as a result.
With next generation wireless and digital media devices requiring larger program size, increased local frame buffers and efficient multi-tasking, CEVA-TeakLite-III expands its predecessor's memory addressable space by offering a 4 GB address space for code and data memory. The core also offers a 32-bit unified general purpose register bank and a 32-bit integer unit, with bit manipulation and quick look-up-table access capabilities, as well as a branch prediction mechanism, to further enhance its micro-controller feature set.
CEVA-TeakLite-III is a fully synthesizable soft core and a process-independent design that allows licensees to specify the silicon area, power consumption and speed that best suits their needs.
Development Tools and Supportv As with all CEVA solutions, CEVA-TeakLite-III is supported by a robust development environment that includes a highly efficient C/C++ compiler, an advanced GUI debugger, a built-in instruction set and cycle accurate simulators, a complete set of binary tools, and a profiler to measure performance. The development tools run on Windows, Solaris and Linux, and are supported by a worldwide customer service team. CEVA-TeakLite-III is further complemented by extensive algorithms and applications from CEVA and the CEVAnet third-party development community.
CEVA-TL3210 and CEVA-TL3214 are two specific configurations of the CEVA-TeakLite-III architecture that are available for licensing today. The CEVA-TL3211 will be available for licensing in early 2008.
CEVA-TeakLite-III Live Webinar
On June 13th, CEVA will conduct a live webcast presentation introducing the new CEVA-TeakLite-III DSP architecture. This webinar will take place at 10:00 AM Pacific / 13:00 PM Eastern / 17:00 PM GMT. Following the webcast, the presentation will be available on demand from the TechOnLine website. To register for the webcast, go to http://seminar2.techonline.com/registration/distrib.cgi?s=1093&d=964
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is a leading licensor of innovative intellectual property (IP) platform solutions and DSP cores for wireless, consumer and multimedia applications. CEVA's IP portfolio includes comprehensive platform solutions for multimedia, audio, voice over packet (VoP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA), and a wide range of programmable DSP cores and subsystems with different price/performance metrics serving multiple markets. In 2006, CEVA's IP was shipped in over 190 million devices.
For more information, visit http://www.ceva-dsp.com