SANTA CLARA, Calif. Altius Solutions Inc. has unveiled its new design services model and become the second company this month to announce a tool that allows engineers to convert hard intellectual property (IP) blocks into gate-level functional models, which in turn can be remapped with synthesis tools into new designs.
Joseph Costello, the former president and chief executive of Cadence Design who is now a member of the Altius board, said Altius will offer the design services equivalent to the silicon foundry services model pioneered by the likes of Taiwan Semiconductor Manufacturing Co., United Microelectronics Corp., and Chartered Semiconductor.
"Several years ago companies like TSMC and UMC popped up with this new business model for a new way to make ICs," Costello said. "At first they were laughed at and now they have multibillion-dollar [market] caps. Altius offers a design foundry capability like that of the silicon foundry compa nies."
Costello said it became evident before he left Cadence that traditional ASIC design methodologies weren't going to cut it for system-on-a-chip (SoC) design because there were new electrical issues with new processes and a design groups required the right mix of circuit-and system-savvy designers.
"It was becoming clear that ASIC methodologies just didn't scale up for system on chips," said Costello. "What is needed is a new way of doing things that is what Altius' SoC Design Foundry service is all about."
Aurangzeb Khan, president and chief executive officer of Altius Solutions, said his 32-person company has had four consecutive quarters of profitability since its 1999 creation. He said much of this success came from Altius' IP Foundry services, part of the SoC Design Foundry service, helping Cirrus Logic and Stream Machine extract blocks from their legacy designs and reuse their blocks to quickly create second generation products.
Khan said where one unnamed customer took 12 months to develop its first product, the second-generation product using Altius services took fewer than three months to complete. He said time to volume went from 3 to 2 months, and where the first product required 70 engineers, it only took 10 engineers to complete the second-generation product.
He said the IP Foundry service included creating, characterizing and optimizing blocks for next generation products implemented on newer process geometries. Khan helped devise the reuse methodology at Cirrus Logic and then in early 1999 got some backing and created Altius.
The company is productizing the tools it uses for its IP Foundry services. The first of these products is the model creation third of a three-tool product line called IP Station. Khan calls the first offering IP Station Characterize because it allows engineers to create a functional timing model from a Spice netlist.
The company plans to expand this offering with IP Station Analyze and la ter with IP Station Optimization. Khan said the Analyze tool will analyze a layout to find nets that can be adjusted for better performance and the Optimization tool will implement those changes.
"We have one tool ready for alpha testing and we are working on making the second tool a bit easier to use," said Khan. "We have to add a GUI and other features."
In the meantime however the company said its IP Station Characterize will be released in July.
Khan said the tool is targeted at system, semiconductor and IP vendors who want to reuse their hard IP or build IP repositories.
"A lot of companies want to reuse blocks of their chips for their next product but they find that the engineers on the original design team did not keep records, are busy on other designs or perhaps moved on to a new company," said Khan. "IP Station Characterize makes this a non factor because customers can make a timing accurate gate level model from Spice. Or if companies don't have the people available, they can hir e our IP Foundry services and we can do it."
The announcement IP_Station Characterize functional model generation tool follows a similar announcement made in mid May by Circuit Semantics.
Gary Smith, chief EDA analyst at DataQuest Inc., calls the Altius tool the next step in model generation technology.
Kinying Kwan, vice president of engineering at Altius, said the IP_Station characterization creates from a Spice netlist a functional gate level model within 5 percent accuracy of Spice. This model in turn can be re mapped with a synthesis tool and implemented in a second-generation design.
Khan said IP Station Characterize accepts a Spice netlist, technology files, and DSPF from an RC analysis tool. IP Station Characterize then does a delay calculation and feeds results into static timing analysis to produce a timing accurate functional model.
Khan said unlike competing tools, IP_Station is highly automated, embeds timing in the m odel and checks to make sure the model is electrically correct. According to Khan, the primary feature of the tool is its automatic function recognition engine.
"We don't use pattern matching like other tools and we don't rely on somebody to tell us what a piece of circuitry does," said Khan. "The tool figures it out automatically, including register and sequential elements.
Khan said the tool includes a patent pending ECSM model that instantaneously calculates timing and power.
"Our tool uses an algorithm that manages memory so that isn't really an issue," said Khan. "Our tool is also hierarchical and can handle million gate blocks with no problems."
The Altius IP_Station characterize tool is $330,000 for a three-year license running on Unix.