TSMC's advanced packaging capacity is fully booked until 2025 due to hyper demand for large, powerful chips from cloud service giants like Amazon AWS, Microsoft, Google, and Meta. Nvidia and AMD are known to have secured TSMC's chip-on-wafer-on-substrate (CoWoS) and system-on-integrated-chips (SoIC) capacity for advanced packaging.
www.edn.com/, May. 08, 2024 –
Nvidia's H100 chips–built on TSMC's 4-nm process–use CoWoS packaging. On the other hand, AMD's MI300 series accelerators, manufactured on TSMC's 5-nm and 6-nm nodes, employ SoIC technology for the CPU and GPU combo before using CoWoS for high-bandwidth memory (HBM) integration.
CoWoS is an advanced packaging technology that offers the advantage of larger package size and more I/O connections. It stacks chips and packages them onto a substrate to facilitate space, power consumption, and cost benefits.
SoIC, another advanced packaging technology created by TSMC, integrates active and passive chips into a new system-on-chip (SoC) architecture that is electrically identical to native SoC. It's a 3D heterogeneous integration technology manufactured in front-end of line with known-good-die and offers advantages such as high bandwidth density and power efficiency.
TSMC is ramping up its advanced packaging capacity. It aims to triple the production of CoWoS-based wafers, producing 45,000 to 50,000 CoWoS-based units per month by the end of 2024. Likewise, it plans to double the capacity SoIC-based wafers by the end of this year, manufacturing between 5,000 and 6,000 units a month. By 2025, TSMC wants to hit a monthly capacity of 10,000 SoIC wafers.