Synopsys and Silicon Metrics Deliver Memory Characterization Solution for System-on-Chip Design

MOUNTAIN VIEW, Calif. & AUSTIN, Texas--(BUSINESS WIRE)--Dec. 11, 2001--  Synopsys, Inc. (Nasdaq:SNPS - news) and Silicon Metrics Corporation today announced the availability of their memory characterization solution based on Synopsys' NanoSim(TM) multi-level mixed-signal simulator and Silicon Metrics' SiliconSmart MR(TM). The solution leverages the NanoSim hierarchical array reduction (HAR) technology and the SiliconSmart MR memory characterization and modeling tools to deliver production-ready memory models for system-on-chip (SoC) design.

Most of today's SoC designs contain multiple embedded memories ranging in size from a few to hundreds of kilobytes. To jumpstart their SoC design, designers often look to compiled memory models that must be re-characterized to ensure they are bug-free and production-ready. Together, NanoSim and SiliconSmart MR offer a fully-automated solution that handles this memory re-characterization efficiently and produces highly accurate results.

"NanoSim's unique HAR technology allows entire memories to be simulated quickly and accurately without netlist pruning. This makes NanoSim a very attractive platform for SiliconSmart MR," said Callan Carpenter, president and CEO of Silicon Metrics. "Given the level of pain associated with memory characterization today, this solution offers customers an immediate and significant ROI."

SiliconSmart MR and NanoSim bring tools to the SoC designer's desktop for characterization setup and simulation that make it easy to acquire high-quality models for embedded memories. Plus, SiliconSmart MR reads and writes timing models in the industry-standard Synopsys Liberty(TM) (.lib) format, speeding re-use in downstream applications.

"NanoSim is the trusted full-chip multi-level simulator for mixed signal and memory design verification," said Antun Domic, senior vice president, Synopsys' Nanometer Analysis and Test Group. "The combination of SiliconSmart MR and NanoSim delivers high-quality, accurate timing and power models for Synopsys design flows. We encourage our customers to consider SiliconSmart MR and NanoSim for embedded memory characterization and modeling."

About Silicon Metrics Corporation

Silicon Metrics Corporation is a privately held company based in Austin, Texas. The company has offices in Austin and San Jose, California. Marubeni Solutions represents Silicon Metrics Corporation in Japan. Company investors include Austin Ventures, Needham Capital Partners, Current Ventures, Cadence Design Systems (NYSE:CDN - news), and Synopsys, Inc. (Nasdaq:SNPS - news). The Silicon Metrics team brings decades of combined electrical engineering and electronic design automation (EDA) experience to bear on the challenge of eliminating silicon respins caused by timing flaws. For more information, call 888/828-3736, or visit Silicon Metrics online at http://www.siliconmetrics.com.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS - news), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys is a registered trademark and NanoSim is a trademark of Synopsys, Inc. Silicon Metrics, the Silicon Metrics logo, and SiliconSmart are trademarks or registered trademarks of Silicon Metrics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.