Leading Verification IP (VIP) Increases Quality, Speeds Verification; OCP ABVIP Already Used on Over 75 Verification ProjectsBEAVERTON, Ore. -- July 09, 2007
-- The Open Core Protocol International Partnership (OCP-IP), an independent non-profit semiconductor industry consortium, today announced their support of Cadence’s Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. OCP’s ascendance as the system architecture “backbone” within increasingly complex consumer and portable designs has driven the need for improved verification at the block, chip and system levels.
Engineers performing verification for OCP typically require both compliance and cover checks to efficiently verify relevant protocol scenarios. Cadence’s ABVIP is used for interface monitoring in simulation as well as exhaustive formal analysis of OCP implementation including compliance. OCP-IP is taking important steps to alleviate these design challenges by supporting the ABVIP from Cadence.
“By recognizing Cadence’s assertion based ABVIP we are taking further strides in enhancing the supporting infrastructure surrounding the standard. OCP designers can leverage a customer proven product from an industry leader well versed in VIP development and methodology,” said Ian Mackintosh, president of OCP-IP. “Cadence has been focusing on VIP development for quite some time and has applied its experience to deliver high quality VIP for the OCP standard.”
OCP has gained wide acceptance as an on-chip interface because designers can adopt the standard rapidly and easily integrate OCP-compliant blocks into the broader SoC. As these designs grow increasingly complex with larger numbers of blocks and multiple interfaces, it is even more critical that the blocks or modules be verified early in the design cycle. This enables bugs to be detected when they are easiest and least expensive to eliminate. At this stage of the design such work is typically done by engineers (vs. verification specialists) thereby requiring VIP that works in the absence of a testbench. Cadence’s assertion based OCP VIP fits this bill perfectly since it requires no stimulus and can be used in both simulation and formal verification.
“We want our customers to have access to verification IP that provides the highest quality and most predictable path to successful tapeout,” said David Tokic, Strategic Marketing Director at Cadence. “At Cadence we’re once again empowering design teams to increase quality and maximize their productivity by using mature ABVIP for the configurable OCP protocol.”
Cadence’s assertion based VIP broadens their OCP solution as it can be used in conjunction with (or separately from) the complementary OCP UVC provided by Yogitech, a Cadence Verification Alliance member and a leading supplier of OCP verification solutions. The OCP UVC is a functional VIP supporting multi-language verification environments including SystemVerilog. The UVC is built upon a core technology which has been adopted by leading semiconductor vendors and has years of use in multiple designs. With this full Plan-to-Closure solution, Cadence customers have access to OCP VIP for the full scope of their project from block to chip to system level verification.Availability and Pricing
Cadence Verification IP is available today and can be downloaded from the Cadence website at: http://downloads.cadence.com
. Pricing is determined based on quantity licensed. For a single unit pricing for a one year license is $15,000.About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering Committee participants include: Nokia [NYSE: NOK], Texas Instruments [NYSE: TXN], Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs. VSIA endorses the OCP socket, and OCP-IP is affiliated with VSIA. For additional background and membership information, visit www.OCPIP.org
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com