Verdi Debug System Takes on Bigger, More Complex Chip Designs, Enables Further Automation of SystemVerilog Assertion and Testbench Debug SAN JOSE, Calif. -- July 9, 2007
-- Novas Software, Inc., the leader in debug and visibility enhancement solutions for complex chip designs, today detailed its roadmap for the continuing evolution of its debug automation platform for large digital ICs and systems-on-chip (SoCs). The Novas platform unifies the languages, abstractions and tools needed to cut in half the time it takes to understand and debug design behavior starting from system-level specification through silicon implementation. Novas' latest advancements are expected to deliver three to ten times more performance and capacity across the entire platform, and fuel adoption of SystemVerilog-driven verification methodologies with more automated debug solutions.
Performance initiatives are focused on enabling fast, fine-grained access to critical portions of big designs and new incremental, on-demand approaches that accelerate automated analysis and tracing capabilities. Novas is also building on its comprehensive SystemVerilog infrastructure with enhanced SystemVerilog Assertion (SVA) debug solutions and source code debug support for SystemVerilog Testbench (SVTB) descriptions. These capabilities are being rolled out with quarterly releases of Novas' award-winning Verdi(TM) Automated Debug System starting this month.
"Chips are getting bigger with over 100 million gates and approaching one billion transistors. This creates an astronomical challenge for the engineers trying to comprehend the complex structure and behavior of these designs," said Scott Sandler, president and CEO of Novas Software. "We're scaling the performance, capacity and capabilities of the Verdi debug platform to keep pace with design size and complexity. Our customers can adopt the latest standards and methodologies with confidence in their ability to debug the largest, most complex SoCs."
Larger Designs, Faster Debug
Novas has modified the underlying structure of its de facto industry-standard fast signal database (FSDB) to both improve the raw speed of data retrieval and provide more efficient access mechanisms throughout the system. The immediate impact on response times and memory utilization is impressive:
- 5X improvement when adding signals to the waveform display;
- 2X - 10X improvement for tracing in source code and schematic views with annotated signal values; and
- 3X improvement when comparing large FSDB files.
Novas is also enhancing debug productivity with incremental, on-demand creation of specialized databases to support more advanced features. These include module-based behavior analysis performed incrementally at the block-level in just seconds and a signal-based schematic database for 10X faster visualization and tracing of large flat netlists using 3X less memory. Future enhancements will apply the on-demand model to Novas' knowledge database (KDB) to speed the loading and interactive processing of design data. Further optimization of FSDB data handling techniques is also expected to yield significant additional improvements.
Industry trends point toward broader user adoption of the SystemVerilog language as the standard for assertion-based verification and testbench creation. Novas is evolving its debug platform with new SVA and SVTB capabilities that address the abstract and dynamic nature of these methodologies. Key elements include:
- SVA - Fast off-line assertion checking; assertion analysis engines to automatically isolate failures; and on-the-fly, post-simulation calculation of assertion data to speed debug and minimize simulation data capture requirements.
- SVTB - Traditional source code visualization and tracing; advanced browsers for viewing class structure and hierarchy; and new visualization and analysis engines for the capture, display and tracing of dynamic data and class structures.
Pricing & Availability
Initial performance and capacity upgrades and SVA analysis capabilities are immediately available with the latest release of the Verdi Automated Debug System. Enhanced SVA solutions and SVTB source code debug will follow starting in the third quarter of 2007. Advanced SVTB features will be introduced through early 2008. The Verdi debug system is list priced at US$14,000 for a one-year subscription license.
Novas Software, Inc. is the leading provider of design comprehension solutions that enhance verification of complex ICs, embedded systems and SoCs. The Novas Verdi(TM) Automated Debug and Siloti(TM) Visibility Enhancement products cut debug time in half while dramatically minimizing simulation overhead. Novas is headquartered in San Jose, Calif. with offices in Europe, Japan and Asia-Pacific. For more information, visit www.novas.com or email firstname.lastname@example.org.