LONDON Co-Design Automation Inc. (San Jose, Calif.), an EDA startup that has developed a system-level hardware design language to raise design abstraction and improve productivity, has announced its first two EDA offerings: the SystemSim simulator and SystemEx extraction tool.
Although Co-Design had been expected to launch a simulator specifically for its Superlog language, it has instead produced a broad simulation engine that simulates designs described in multiple languages. Beyond simulating Superlog code, SystemSim can accept C and C++ in general (and the Open SystemC version of C++ in particular) as well as the Verilog hardware description language, including its latest refinement, Verilog 2000.
In the second half, SystemSim is slated to expand support to the VHDL hardware description language and to SpecC, a C variant that supports the conversion of informal, natural-language system definitions into executable specifications. As p art of the planned support for SpecC, Co-Design has joined the SpecC Technology Open Consortium.
SystemSim is complemented by SystemEx, which can transform more abstract system descriptions into synthesis-ready HDL code. SystemSim is priced at $40,000 and SystemEx at $25,000 per seat. Both tools run under the Sun Solaris and Linux operating systems.
The major claim for SystemSim, beyond its being the first tool to support the Superlog language, is that it allows multilingual simulation without the inefficiencies associated with the use of conventional programming language interfaces (PLIs). Co-Design's literature claims the effect is "design in half the time at one-third the cost."
"The key issue is the efficiency with which these languages can be used together, and that is what Co-Design has focused on with our new simulation products," said Simon Davidmann, president and chief executive officer.
The company claims SystemSim can provide a simulation performance improvement of two orders of magnitude while offering mixed simulation of Verilog, Superlog and other languages.
The Superlog language, written mainly by Peter Flake, chief technology officer at Co-Design, is intended to combine the best constructs of Verilog and C for high-level design. But Davidmann said it is inevitable that hardware design elements in multiple languages will coexist for the foreseeable future.
Once designers have simulated a design at the system level using SystemSim, they can use SystemEx to extract those parts of the design that can be expressed in Verilog, Superlog or C.
"SystemEx not really a synthesis tool, nor is it intended as a language translator, although it can do some of that," said Davidmann. "The main reason for SystemEx at the moment is as a stop-gap until downstream tools accept Superlog."
A number of startup and established EDA companies are members of the Superlog-2000 partners program and are working with Co-Design to produce synthesis tools that will operate on Superlog descriptions.
Davidmann said SystemSim's good mixed-language performance stems from a couple of language-handling advances, dubbed CBlend and parallel instruction optimization. The CBlend technology enables multilingual support for C, C++, Verilog and Superlog without the use of PLIs, which can slow overall simulation.
"In other linked simulations, the overhead to call C function is one line to write the call and 30 lines or more of setup," said Davidmann. "In SystemSim, all of the setup of threads and pipes is done automatically, 'under the hood.' Also, we can call Verilog code from C, and things like shared variables, naming conventions and data-type conversions are handled by C-Blend."
Harald Bergh, chief executive officer of FreeHand Communications AB (Stockholm, Sweden), a developer of DSP cores for voice recognition apps, offered a user's perspective. "By eliminating interface overhead, SystemSim has enabled a clean and highly efficient integration of our DSP instructio n set simulator model," Bergh said. "This no-PLI approach to model integration allows us to easily incorporate the C-based ISS model into a multilingual HDL/C design environment."
The parallel instruction optimization allows simulation to approach typical compiled code for behavior and algorithmic models, while maintaining the interactivity associated with interpreted simulation.
Davidmann said SystemSim would benefit all design groups that need to use multiple languages, even if they do not use Superlog, although he acknowledged that some of the SystemSim beta sites were existing Superlog users.
"The clarity of this language dramatically reduces the probability of inserting obscure bugs," said Jon Beecroft, principal consultant at Quadrics Supercomputers World Ltd. (Bristol, England). "Superlog offers constructs that allow the compiler to find many of the problems that normally require days of simulation."
Proprietary language, for now
Superlog remains proprietary to Co-Desig n, and engineers wishing to write in the language must sign a nondisclosure agreement to access the language reference manual. But Davidmann said the company still intends to put the language into the public domain later this year, once certain refinements are completed.
In use, the SystemSim simulator is typically driven from a command line interface with text-based presentation of results. But it is equipped with a graphical user interface and debug environment called SystemView, which was licensed from Summit Design (now Innoveda) and has been customized to serve SystemSim.
Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.), said that while he hasn't yet studied SystemSim and SystemEx in detail, he believes Co-Design is "headed in the right direction. They have a clear idea of where the market is going; they are not wrapped up in the idea that C will do everything. And they'll eat any language you care to throw at them.
"Ultimately, what Co-Design wants to win is Superlog seat s," Smith said. "But the adoption of a new language . . . could take two or three years. This is the most sensible approach they could take. They're going to sweep up the mess left by all the legacy code."
Nonetheless, Smith argued that Superlog's full potential will not be realized until there is also support for Superlog-based synthesis a process Co-Design is leaving to partner EDA companies. "RTL design was enabled by the meeting of Verilog from Cadence and Design Compiler from Synopsys. This [Superlog] is pretty much the same approach," said Smith.