Breakthrough approach to reducing variability demonstrated in silicon
Santa Clara, CA—July 18, 2007—Lightspeed Logic, the leading provider of mask reconfigurable IP, today announced that STMicroelectronics has selected Lightspeed Logic’s Reconfigurable Logic IP for use at 65nm and below. In addition to providing increased flexibility in chip architecture, significant reduction in design cost and rapid time-to-market, the regular structure of the tile-based architecture helps reduce lithography and stress-related variability challenges at nanometer scale process nodes.
“Lightspeed Logic’s tile-based architecture allows us to eliminate many variability-related issues up-front, creating litho-friendly logic while gaining the flexibility advantages of reconfigurable logic” said Philippe Magarshack, Group Vice President and General Manager of Central CAD & Design Solutions, STMicroelectronics. “This DFM-friendly approach allows quick introduction of added-value IPs, with a competitive advantage on yield, in new technology node like 45nm.”
“ST’s visionary commitment to be on the leading edge of design technology has been proven again by their commitment to using Lightspeed Logic’s Manufacturability Optimized Reconfigurable Logic in their nanometer scale processes. The silicon results we are seeing validate this decision.” said Dave Holt, President and CEO, Lightspeed Logic. “ In addition to improved yield, we are able to create much more accurate timing models as all proximity and edge effects can be accurately calculated and accounted for due to regularity of the tile-based architecture.”
The Manufacturability-Optimized Logic enables faster process debug and ramp up and delivers higher yields after the process has been stabilized. The addition of these new capabilities to the high-density achieved by Lightspeed Logic’s Reconfigurable Logic IP will produce a higher number of known-good dies per wafer and effectively outperform the equivalent density of standard cells. Customers deploying Lightspeed Logic’s new Manufacturability-Optimized Logic can isolate the front-end and physical design engineers from the complex post-GDS manipulations and prevent the iterations between manufacturing and design typically experienced in advanced geometries.
About Lightspeed Logic
Lightspeed Logic is a provider of mask reconfigurable intellectual property (IP), a digital logic implementation technology that provides time-to-market, yield, manufacturability, and development expense advantages over standard-cell implementation. Founded in 1996, Lightspeed Logic has developed and brought to market four mask-reconfigurable architectures, the most recent of which is a regular logic structure available for multiple foundries, IDMs and process nodes. The company is currently working with customers at the 150, 90, 65, and 45 nm process nodes. Lightspeed Logic’s corporate headquarters are in Santa Clara, CA. You can find more information on Lightspeed Logic at www.lightspeed.com.