Silicon Interfaces ships the new SI16FWA20 Link Layer Controller Fire Wire IP

CAMPBELL, Calif. -- August 2, 2007 -- Silicon Interfaces, a leading design and verification services provider and developer of IPs in Europe, North America and Asia-Pacific, under their IP Development Program - Silicon Cores: Core to the Intelligent Systemsâ„¢, today announced that it has begun shipping its new SI16FWA20 Link Layer Controller Fire Wire IP.

Silicon Interfaces Link Layer Controller core is a functional block available for insertion into an ASIC design, which supports the IEEE 1394a-2000 Draft specifications for a high-speed serial bus. The SI16FWA20 Link core is implemented using VHDL synthesizable code to provide portability across Silicon Interfaces Gate Array and Cell-Based ASIC technologies.

SI16FWA20, 1394a-2000 Link Layer Controller Core provides data packet delivery service for Asynchronous and Isochronous (real-time) data transmission. It performs arbitration request, packet generation and checking, as well as data and acknowledgement transmission. Packet Generation includes setting up of Packet Header, Address, Data CRC, Packet Channel, Destination Address and Transaction Code. Silicon Interfaces Link Layer Controller core also provides complete support for bus Cycle Master and cycle control operation. SI16FWA20 is designed to support 100, 200 and 400 Mbps transmission, when used with the appropriate external Physical Layer device. This depends on the speed provided with a 2-bit, 4-bit or 8-bit interface, which does not require special high-speed buffers. Besides, this version supports the generation of LPS (Link Power Status) signal, based on the current mode in which the device operates (Differentiated or Undifferentiated).

Product Specifications:

• Modes: Asynchronous, Asynchronous Stream and Isochronous Stream
• Core: Fully synthesizable Register Transfer Level (RTL) VHDL
• Test Environment: Reusable Verilog with abundant scenarios
• Targeted FPGA: Xilinx Virtex-4
• Clock Frequency: 50 MHz
• Options:
• Adaptations:
• 32-bit PCI Host Interface possible
• Interrupt-driven Host Interface
• Add-ons:
• Generic 32-bit Host Interface
• An elaborate test suite containing assorted packets and sizes

SI16FWA20 is a highly integrated single-chip core Silicon Interfaces Intellectual Property and represents the company’s proven Link Layer design experience as well as expertise in the field of complex designs. The complete modular design of SI16FWA20 core facilitates easy customization to include value added features.

Please visit the Silicon Cores web site at www.siliconcores.com, for a complete listing of features and pricing of SI16FWA20 Link Layer Controller Fire Wire IP.

Availability

The SI16FWA20  Link Layer Controller IP is available now.

About Silicon Interfaces

Silicon Interfaces has experience in verification solutions and developing IPs for Fabric Channel Interconnect, Telecom and Networking domains, including Bluetooth Baseband, Gigabit Ethernet MAC, SONET Framer STS-1/3, 1394, USB2 Function Controller, USB On-The-Go, USB 2.0 OVA Checker AIP, Infiniband, 8530, 8051, 7990, UART, Rapid IO , 802.11 a/b/g MAC, PCI-Express, 10 Giga and SONET STS Framer –12. These IP have had considerable maturity based on certification, targets to various FPGA devices and ASIC libraries, silicon area optimization, silicon prototyping and testing. Also available are OVA VIPs and an extensive driver development program which enables the company to offer a packaged solution to the customer. For more information please visit www.siliconcores.com