Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
OCP-IP and Nexus Announce Collaboration on Industry Standard Debug Efforts
OCP-IP sponsors an active Debug Working Group focused on problems and approaches related to improving standards based multi-core debug. The Debug working group has recently announced the availability of a white paper discussing a standardized Debug Interface Socket and OCP-bus compliant debug interfaces for IP blocks and cores to support on-chip core, multicore, and systems analysis and debug needs for software, hardware, and mixed SoC prototyping. The OCP-IP Debug strategy will be compatible with complementary industry standards efforts, with initial focus on JTAG (IEEE1149.1) and Nexus (IEEE-ISTO 5001(TM)) interfaces.
"Nexus members include many of the leading companies in the areas of embedded systems debug, many of whom are also members of OCP-IP," said Ian Mackintosh, president OCP-IP. "By collaborating with the Nexus 5001(TM) Forum, we ensure that the work of both groups remains compatible and complimentary in progressing to provide cohesive and complete, end to end debug solutions."
The Nexus 5001(TM) Forum was created in 1999 and is focused upon on-chip debug solutions based on the IEEE-ISTO 5001(TM), the Nexus 5001(TM) Standard for a Global Embedded Processor Debug Interface. Nexus based solutions provide a standard for high performance real-time multi-core debug, trace, calibration, rapid prototyping and on-chip analysis that has been proven in chip designs by several member companies on multiple architectures.
"By coordinating the Nexus and OCP-IP debug activities, customers will see improved core debug interfaces and new debug features that leverage the OCP-IP Debug Interface Socket and Nexus' high performance interface standards," said Dr. Neal Stollon, President of HDL Dynamics, which has been involved with both groups and is developing debug solutions based on both the OCP-IP Debug Interface Socket and the Nexus interface.
To download a copy of the OCP-IP debug white paper, click here.
To download a copy of the Nexus white paper and specification, visit http://www.nexus5001.org.
About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering Committee participants include: Nokia (NYSE:NOK - News), Texas Instruments (NYSE:TXN - News), Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs. For additional background and membership information, visit www.OCPIP.org.
About Nexus 5001(TM) Forum
The Nexus 5001(TM) Forum was formed in 1999 and its membership spans the semiconductor, development tools and automotive electronics industries. Although the Forum initially focused on the stringent requirements of microprocessor debug tools for automotive powertrain applications, its overall goal is to enable the improved development of state-of-the-art, easy-to-use, high-performance processor and SoC analysis architectures and tools. The Nexus 5001(TM) Forum is a program of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). For additional background and membership information, visit http://www.nexus5001.org.
|
Related News
- OCP-IP Releases OCP Debug Socket Specification 2.0
- OCP-IP Announces New Debug Specification
- Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development
- OCP-IP Releases OCP 3.1 Specification into Member Review
- OCP-IP Highlights Successful Implementation of Advanced OCP Features in Leading-Edge Designs
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |