Improves Accuracy and System-Level Functionality
SAN JOSE, Calif. — August 27,2007 — LogicVision, Inc., a leading provider of test and yield learning capabilities for the semiconductor industry, today announced major enhancements to its industry-leading embedded SerDes test solution to help customers cope with the cost and challenges of testing multi-channel, high-speed, serial I/Os. The new release provides more accurate measurements and the ability to perform bit error rate testing (BERT). About LogicVision Inc.
High-speed data serialization/de-serialization I/O technologies, typically known as SerDes, are being rapidly adopted in data storage, telecommunications, and personal computer applications because they offer reliable, low power, high data-bandwidth capability using low-cost backplane and connector technologies. Significant test challenges have emerged as multiple SerDes transceivers, with data rates of up to 10 gigabits per second (Gbps), are being integrated into SOCs. As a result, IC manufacturers are finding it increasingly expensive and time-consuming to guarantee the critical signal-integrity parameters of these high speed I/Os, especially while ramping-up yield.
LogicVision’s Embedded SerDes Test product, ETSerdes™, is the industry’s only vendor-independent, RTL-synthesizable parametric built-in self-test (BIST) for multi-gigahertz SerDes I/Os. It provides unique capabilities for testing ICs with any number of high-speed serial data channels operating at any frequency, from less than 1 Gbps to more than 10 Gbps. ETSerdes provides test accuracy comparable to that of the highest performance external equipment at a fraction of the cost and is compatible with any ATE platform. The ability of ETSerdes to diagnostically measure wave shape, jitter, and jitter tolerance parameters, each in millisecond test times, can drastically reduce test costs and improve quality. All of its capabilities can be re-applied at system-level to quickly characterize entire signal paths.
The previous release of ETSerdes IP rejected asynchronous noise from its delay measurements by averaging out the noise; the latest release is enhanced to also reject synchronous noise (which can not be reduced by averaging). This enhancement ensures that the many clock-related noise sources on-chip, especially from pin signals switching at or below the data’s parallel-rate, have minimal impact on the picosecond delay measurement accuracy of ETSerdes.
Additionally, ETSerdes now includes an industry-standard BERT that can be controlled and monitored via a JTAG port or on-chip system signals. The BERT generates and receives a standard 7-bit based, pseudo-random bit sequence (PRBS7), or a customer-chosen PRBS, to functionally corroborate and extend the existing sub-picosecond resolution jitter and jitter tolerance tests. This embedded capability provides a typically mandatory system-level function, with system and test bus access, and includes automated test generation for quantifying signal path bit error rate (BER).
“As the industry adopts multi-lane, higher-speed serial I/Os, there’s a need for cost-effective test strategies that scale with device performance and complexities,” said Farhad Hayat, VP of Marketing at LogicVision. “The latest enhancements to ETSerdes accommodate the increasing levels and types of noise on today’s nanometer ICs and deliver more test capabilities for reuse in the end-application.”
ETSerdes version 6.0a is in full production and available immediately.
LogicVision (NASDAQ: LGVN) provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com