Cavendish Kinetics Names Richard Knipe VP of Engineering & CTO
Industry Veteran Joins Executive Team
SAN JOSE, Calif -- September 12, 2007 -- Cavendish Kinetics, the Nanomech(tm) embedded non-volatile memory intellectual property (IP) company, announced today that Richard Knipe has joined the company as Vice President of Engineering and Chief Technology Officer.
"Richard is an excellent addition to our executive team," said Dennis Yost, CEO of Cavendish Kinetics. "He brings a wealth of experience in development, transferring technology into volume production and building first-class engineering organizations. The timing is perfect for Richard to move Cavendish's Nanomech embedded non-volatile memory forward."
Dr. Knipe brings over 22 years of semiconductor industry experience to Cavendish Kinetics. In his most recent assignment at Texas Instruments, he served as the Business Manager for the DLP Optical Networking and Digital Sensor Groups. In addition, he has held other senior management positions at Texas Instruments and was responsible for bringing the very successful Digital Light Processing (DLP) technology out of development and into production. Dr. Knipe holds a Ph.D. in Mechanical Engineering from the University of Texas at Arlington and holds over 20 patents.
"Cavendish Kinetics is in an excellent position from a market, technology and people position to be a leader in the marketplace," said Richard Knipe. "The company has a great opportunity to change the landscape of embedded non-volatile memory and I look forward to contributing to its success."
About Cavendish Kinetics
Cavendish Kinetics is a fabless semiconductor IP company developing embedded Non-Volatile Memory technology for standard CMOS processes. Its Nanomech™ technology is a novel non-volatile memory solution, residing in the metal interconnect system, yielding no impact to existing IP, scaling to 45nm and below, operating beyond 200 degrees centigrade in a radiation harsh environment, and porting easily to different process technologies. Nanomech programs at high-speed and at native voltage requiring no high voltage overhead. It has ultra low-power write/erase and read with no leakage current. The base technology has been silicon proven and it has demonstrated 20M-cycle endurance. For more information please visit http://www.cavendish-kinetics.com.
|
Related News
- Green Plug Appoints Kevin Jones to New Post of Chief Scientist, Names Rajeev Prasad VP of Engineering
- Innovative Silicon Names Daniel LaBouve VP of Engineering
- LogicVision Names George Swan VP of Engineering
- EdgeCortix Expands Leadership Team by Appointing Jeffry A. Milrod as Vice President of Product Engineering
- Veriest Solutions Promotes Dusica Glisic to Vice President of Frontend Engineering
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |