Lexra spins six-stage processor core

Lexra spins six-stage processor core
By Michael Santarini, EE Times
April 21, 2000 (6:31 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000421S0043

SAN MATEO, Calif. — Lexra Inc. next week will launch its 32-bit RISC LX4189, a six-stage pipeline version of its microprocessor core, in an effort to drive its devices into the hot communications markets. The company also has drastically cut pricing of its earlier offering, the LX4180 core.

Plans to move even deeper into communications are set for June, when the company will launch a third product line.

Charlie Cheng, president and CEO of Lexra, said the LX4189 is the first RISC six-stage core released to the market, beating ARM's five-stage processor, the ARM10, and the Intel-ARM jointly developed seven-stage part, the StrongARM II, by six months.

The six-stage pipelining also gives the core a 30 percent speed edge over other five-stage RISC cores, such as the ARM9S and MIPS 4000, the company said.

Until now, the LX4180 series of processors and competitive equivalents have been targeted at the consumer market, because of clock s peeds as low as 100 MHz. But the LX4189, which has a worst-case clock rate of 266 MHz, is fast enough to do housekeeping chores for communication applications, like Voice over Internet Protocol (IP) and edge routers, Cheng said.

"When customers move from 0.18 and 0.15 [micron], there is a big problem linking the housekeeping processor to the main data path," said Cheng. "When you're designing a 250-MHz Voice over IP [system], for example, you need a housekeeper MCU that will run at comparable speeds."

Previously, said Cheng, designers using 100-MHz cores in 250-MHz applications have had to add expensive phase-locked loops and asynchronous logic to have the core initialize the rest of the chip and perform such functions as error recovery, which complicates the design.

"The clock speed makes the design simple, reduces the risk of bugs and, therefore, reduces time-to-market," Cheng said.

The core consumes roughly 65,000 gates and is 1 mm2 on 0.15-micron processes. It issues one instruction per c ycle and, at the 266-MHz worst-case conditions, offers between 230 and 250 Mips, said Cheng. The nominal speed is roughly 333 MHz running at room temperature, he said.

The RTL core is shipping now for a single-project license fee of $350,000.

Cheng said the company is also reducing the price of its LX4180 to appeal to designers in the consumer market.

The company has cut the price of the RTL core to $179,000 per project, while the hard version for TSMC and UMC in 0.25 and 0.18 micron are priced at $279,000 and $369,000, respectively.