Susan Cain and Jim Lipman, Cain Communications (10/02/2007 11:48 AM EDT) -- EE Times
Whenever certain SoC design tasks take on a high level of importance (for example, being on the critical path of design completion), design teams usually add a task-specific manager. Examples include a testability manager (when DFT becomes an important part of chip design), a physical layout manager (when shrinking process nodes and increased clock speeds make layout very difficult), and, more recently, a DFM manager (when help is needed to ensure maximum yields, and profits, for chip vendors). But the question remains: Where is the IP manager?
Integrating several IP cores on an SoC has become a normal part of a design team's activities. The various IP has to meet quality, testability, reusability and other criteria to be used on the chip. Owing to a lack of industry-wide specifications for these criteria, the job of successfully integrating different IP, from several diverse sources, onto a single chip has become more and more difficult. De facto standards for selecting IP and IP vendors, such as the VSIA's Quality IP (QIP) metric and the IP-XACT from the Spirit consortium, are few and far between and are still in flux, although adoption is growing. This creates a need for a person to fill a particular role on an SoC design team: that of IP manager, responsible for overseeing the selection, use and verification of the various IP cores on a chip, someone who is in touch with the various industry organizations that can help the company benefit from available standards.
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