English
SoC design's new normalPlatform push roils business models
Rick Merritt, EE Times
(10/08/2007 9:00 AM EDT)
Santa Clara, Calif. -- A group at Microsoft Corp. is co-developing a media chip and is even investigating new on-chip bus structures. The activity is occurring at a time when semiconductor companies say they are increasingly delivering full software stacks with their chips, although they are not always compensated for the code.
Welcome to the next phase of the system-on-chip era, in which system, software and semiconductor companies are struggling to find new technology and business models. All sides see the promise for using multicore devices to open up fresh markets. The big question is how to define chip-level platforms.
That dilemma lies at the intersection of two developments. Designers increasingly start their work by defining the end-user scenarios or experiences they want to create. As they move to implement those concepts in silicon, they find an increasing diversity of hardware and software components integrated in complex, off-the-shelf chips with varying degrees of programmability, but not always optimized for the chosen tasks.
"We brought a value proposition for a system to a fabless company but found that no [chips] met our requirements, so we had to ask them if we could develop something together," said Robert Rossi, group program manger for core media processing technologies at Microsoft. "We had conversations with their CEO and found out we could do it."
(10/08/2007 9:00 AM EDT)
Santa Clara, Calif. -- A group at Microsoft Corp. is co-developing a media chip and is even investigating new on-chip bus structures. The activity is occurring at a time when semiconductor companies say they are increasingly delivering full software stacks with their chips, although they are not always compensated for the code.
Welcome to the next phase of the system-on-chip era, in which system, software and semiconductor companies are struggling to find new technology and business models. All sides see the promise for using multicore devices to open up fresh markets. The big question is how to define chip-level platforms.
That dilemma lies at the intersection of two developments. Designers increasingly start their work by defining the end-user scenarios or experiences they want to create. As they move to implement those concepts in silicon, they find an increasing diversity of hardware and software components integrated in complex, off-the-shelf chips with varying degrees of programmability, but not always optimized for the chosen tasks.
"We brought a value proposition for a system to a fabless company but found that no [chips] met our requirements, so we had to ask them if we could develop something together," said Robert Rossi, group program manger for core media processing technologies at Microsoft. "We had conversations with their CEO and found out we could do it."
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Algotochip Industry's First Company to Deliver Complete SoC GDSII From C Models of Algorithms
- Canaan's RISC-V based edge AIoT SoC adopted VeriSilicon's ISP and GPU IPs
- Microchip's Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers
- Andes Technology and MetaSilicon Collaborate to Build the World's First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC
- M31 Promotes Advanced SoC Development and Innovation at Intel Foundry's Direct Connect Event
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance