Dolphin Integration announces its ultra low power, low leakage and High density 65 nm ROMs and RAMs
France, October 11, 2007 -- DOLPHIN Integration marks their presence at 65 nm, with the patented tROMet Phoenix, optimized for ultra high density and very low leakage, as well as the spRAM Uranus optimized for Low power and Low leakage.
Typically, the silicon area of a 6-Mbit instance ROM in 65 nm will decrease as far as 0.63 mm2 with only 1.2 uA leakage current, thanks to the key “two-in-one” patent.
For a RAM instance of 64 kbits, the power consumption is a mere 9 uA/Mhz and leakage in power-down mode is 0.91 uA.
More information on http://www.dolphin.fr/flip/ragtime/65/ragtime_65_ram.html
|
Dolphin Design Hot IP
Related News
- DOLPHIN Integration releases a ROM in 65 nm with Ultra high density and ultra low leakage
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- Dolphin Integration announces the availability of a flexible CODEC configuration with ultra low power for providing Nomad systems
- Dolphin Integration releases its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density
- INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
Breaking News
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
- intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
- Sevya joins TSMC Design Center Alliance
Most Popular
- Weebit Nano nears productisation, negotiating initial customer agreements
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
- Sevya joins TSMC Design Center Alliance
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Open Compute Project Foundation and JEDEC Announce a New Collaboration
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |