TSMC weighs pain versus gain in 130-nm technology

TSMC weighs pain versus gain in 130-nm technology
By David Lammers, EE Times
April 19, 2000 (3:18 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000419S0034

HSINCHU, Taiwan — Shang-yi Chiang and his co-workers at Taiwan Semiconductor Manufacturing Co. (TSMC) have a big decision to make over the next six weeks. Chiang, the company's vice president of research and development, is in the final stages of evaluating two low-k dielectric options for the giant foundry company: the carbon-doped oxide Black Diamond material from Applied Materials Corp.; and a pair of spin-on dielectrics — Dow Chemical's SiLK and the Flare material from Honeywell-Allied.

"The low-k dielectrics are not mature at this point," Chiang said. "Some of them peel off, others crack. We evaluated about 50 different materials, and have narrowed it down to three suppliers, but there are still a lot of issues."

Chiang's team must make its pick by June, so that TSMC can "freeze" and qualify a high-performance 130-nanometer (0.13-micron) process over the next year for customers that sell graphics chips, SRAMs and network processo rs. For TSMC's standard 130-nm process, due out late this year, a copper-with-fluorinated silicate glass (FSG) combination will prevail. This so-called "economy" process will coexist with the high-performance process that Chiang and his team are now struggling to define. The latter process is expected to debut in mid-2001.

Like several of its colleagues in the semiconductor industry, TSMC is taking a step-by-step approach to the tricky integration of copper and low-k dielectrics. Late last month it began shipping devices at 150-nm design rules, using all-layer copper wiring with the FSG dielectric.

Wild differences

But the task shapes up differently at a foundry serving 90 customers with wildly different volume and performance needs than it does at a chip maker like Intel Corp. or Texas Instruments Inc., with high-volume product lines to fall back on.

"When all of the fabless companies started cropping up, most of us looked at [the phenomenon] skeptically a decade ago because we didn't think they could take advantage of the best technology," said Vin Dham, a former Intel executive who heads network processor startup Silicon Spice (Mountain View, Calif.). "It was the old thinking of 'real men have fabs.' But now, nobody thinks twice about going to the foundries. [TSMC] will do a copper-with-low-k process that will be as good as whatever TI and others can do, no doubt about it."

TSMC's R&D team first combined copper with silicon dioxide at the 180-nm process node and found almost no performance gain, largely because customers had not optimized routing for the new interconnect stack.

Developing a copper-with-FSG process was challenging, Chiang said, because fluorine atoms tended to break their bonds, float around and interact with copper, with a highly corrosive effect. Late last year, the R&D group came up with a reliable method of containing the FSG, and the copper-FSG combo will be used for customers at 150- and 130-nm design rules.

"Frankly, we don't expect many custom ers to use copper until the 130-nm generation," said Chiang, who spent much of his silicon research career at Hewlett-Packard Co. (Palo Alto, Calif.) before joining TSMC, based here. "At 150 nm we can offer all layers of copper, but only one customer has taped out a chip with all copper layers thus far."

At 150-nm design rules, most customers will stick with aluminum, or will use copper for only the top two metal layers. But TSMC will leverage the learning it gains at 150 nm to propel the move to a copper-only process at 130 nm.

"We made the decision some time ago to go all copper for all layers at the 130-nm node," said Jack Sun, director of logic technology development, who came to TSMC three years ago from IBM Corp.'s process research organization. "We've already crossed that bridge."

The FSG-copper combination, which will be used in prototype production at 130-nm design rules starting late this year, will continue to be the high-volume economy process at TSMC for several years. The crunch c omes for the high-performance process.

Crunch time

"The whole industry has been struggling over the low-k issue," Sun said. "At TSMC, we have a very diverse set of customers that go across the spectrum in terms of their needs. For customers that are not interconnect limited, who just worry about density more than resistance-capacitance delays, the FSG-with-copper process will be a lot more mature, though that has got its limitations."

Because the higher-margin customers are performance driven, TSMC needs to get a high-performance process ready as soon as possible. Thus, the agonizing decision about which low-k material to use.

Saying that a decision must be made "certainly by June," Sun ticked off the pluses and minuses of the spin-on materials vs. those, like Black Diamond, based on chemical vapor deposition (CVD).

"From a tool standpoint, the CVD materials are more compatible with the cluster tools we use," he said. "But TSMC has a lot of experience with spin-ons because w e have used that for the back-end [interconnect] dielectrics in the past. But either way we go, it is a struggle. We are doing a lot of work to integrate copper with our CMP [chemical mechanical polishing] approach. And there are mechanical strength issues that relate to packaging.

"The spin-on materials have adhesion and mechanical issues that could make the integration work very difficult," Sun went on. "For the CVD materials, the question is 'how low can you get?' The spin-ons offer lower 'k' values."

Though both types of materials pose integration problems, the spin-ons "maybe have bigger issues," said Sun. At the same time, "they offer more potential, a lower 'k' and higher performance. That is the no-pain, no-gain kind of question facing us now."

Which customers will be the process drivers for TSMC's high-performance process? Executives are somewhat reluctant to answer that question, in part to guard customer confidentiality. But a few companies are known to be eyeing the 130-nm node.

Graphics powerhouse Nvidia Corp., for example, is moving to the 150-nm process for volume manufacturing by the third quarter, and is a sure candidate to quickly adopt 130-nm technology as well.

In addition, TSMC is in the early stages of producing the Joshua and Samuel processors for Via Technologies Inc., and those integrated processors could move to high volumes, provided intellectual-property squabbles with Intel do not present an obstacle. Also, SRAM vendor GSI Corp. and other fabless SRAM vendors are likely to drive TSMC's 130-nm process technology.

With several new fabs now under construction, TSMC needs to attract volume customers that push the density and performance envelopes. Unlike Intel or Texas Instruments, which have processor and DSP lines to turn to for manufacturing volumes, TSMC itself designs no products — its 90-odd customers do. The foundry keeps about 10,000 mask sets in storage for them, and runs 16 different process technologies.

"The more performance we can offer, the more customers we can get for the process," said Sun.

Many of those performance-hungry customers will come from the networking space, said Ron Norris, TSMC's senior vice president of sales and marketing. For example, TSMC is the announced manufacturing partner for net processor startup Silicon Spice.

While Silicon Spice remains in "stealth mode" about its architecture, Gary Banta, the company's vice president of marketing, said Silicon Spice has decided to move to TSMC's 130-nm high-performance process.

Silicon Spice will use a "contemporary" process at TSMC for its first products, but quickly shift gears into 130-nm design rules as soon as the high-performance process is offered in the middle of next year, said company chief Dham, who spent a week in Taiwan recently at TSMC.

Beyond expectations

"In the past few years, TSMC's process development operation has very consistently over-delivered, going beyond the expectations of their customers," Dham said.

While Silicon Spice and most other customers expect to ship in volumes, some TSMC customers need performance but buy only a few thousand chips per production run. "A mask set at 150 nm can easily cost $200,000 or more, and that is a major concern to our customers, many of which need 10 wafers or less at a time," Chiang said. "One technology we are working very hard on is direct-write electron-beam [lithography]. In some cases customers could use direct-write e-beam only for the most critical mask layers, and in that case we want to match the direct-write e-beam with our own phase-shift-mask process."