Industry Leaders Collaborate to Solve Timing Closure on DDR PHY'sPALO ALTO, Calif. -- Oct. 25, 2007
-- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design, today announced that Cadence Design Systems, Inc., the leader in global electronic-design innovation, has awarded Denali with a "Collaboration Award" for excellence in sales support at the annual Design Chain Partners Event held by Cadence. The award was one of four presented by Cadence to its worldwide network of over 200 design chain partners. Denali was specifically recognized for generating the largest number of high-quality joint sales engagement opportunities throughout 2007.
Denali partnered with Cadence in 2007 using the Cadence® SoC Encounter(TM) RTL-to-GDSII system and Encounter® Timing System to develop a methodology for hardening the Denali Databahn(TM) DDR Hard PHY product line. Throughout the year, Denali has worked closely with Cadence to develop business opportunities resulting from this collaboration. Working with the Cadence OpenChoice business development team at venues such as Design Automation Conference, CDNLive! Silicon Valley, and Denali's Memcon, Denali was successful in generating the largest number of high-quality joint sales engagement opportunities among all OpenChoice partners.
"Since Denali and Cadence decided to work together to address the timing convergence problem on DDR PHY's and provide hardened blocks, the customer response has been outstanding," said Michael Horne, group director, Industry Alliances at Cadence. "Using their PHY compiler methodology with the Cadence SoC Encounter system, our joint solution has unleashed a flurry of customer interest at multiple industry forums, and Denali has been exceptionally proactive in sharing those opportunities with Cadence. It is a working example of successful collaboration in practice."
"We are extremely pleased to have been recognized by Cadence for the effectiveness of our joint sales activities," said David Lin, vice president of marketing at Denali. "Cadence understands the value in supporting the design chain ecosystem, and has engaged with Denali to solve a real bottleneck in implementing DDR memories. We plan to continue working closely with Cadence to address the needs of our mutual customers."About the Denali/Cadence Collaboration
In May of 2007, Denali announced delivery of an advanced DDR-PHY implementation methodology based on the Cadence® Encounter® digital IC design platform. This new methodology uses Cadence SoC Encounter(TM) RTL-to-GSDII system for design and physical implementation and Cadence Encounter Timing System for design closure and final timing, signal integrity and signoff - both are key technologies of the CPF-enabled Encounter platform. For a more in-depth overview of this methodology, view the webcast at: http://www.denali.com/webcast/socencounter/
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND and DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com