LatticeSC FPGAs To Provide Low Cost, Low Power SPAUI to SPI4.2 Bridging Solutions for Dune Networks’ FAPs and Traffic Managers
HILLSBORO, OR & SUNNYVALE, CA - OCTOBER 29, 2007 - Lattice Semiconductor, a leading FPGA provider, and Dune Networks, a provider of networking devices for Data Center, Enterprise and Carrier Ethernet scalable switching platforms, today announced they will collaborate in the development and marketing of SPAUI-based networking solutions.
LatticeSCM™ FPGAs provide an optimized programmable platform to bridge to switch fabrics and traffic managers by utilizing hardened Ethernet and SPI4.2 blocks implemented via exclusive Masked Array for Cost Optimization (MACO™) technology. Dune Networks’ FAP traffic managers provide ingress and egress programmable traffic management solutions that address the requirements of the MEF, IETF DiffServ, and DSL Forum TR-059/TR-101.
SPAUI is a serial interface based on the10GbE XAUI and SPI4.2 standards. By combining the benefits of both into one comprehensive standard, SPAUI enables system designers to take advantage of the ubiquity of XAUI as a physical layer as well as the multi-channel QoS and flow control mechanisms of SPI4.2. SPAUI is also designed to support aggregate rates of higher speeds. SPAUI is one of the interface options of Dune Networks’ SAND chipset.
“Dune Networks welcomes Lattice to the SPAUI ecosystem. The LatticeSCM device’s embedded MACO cores, especially the SPI4.2 core, offer our customers a low cost and low power programmable fabric interface chip option,” said Ofer Iny, CTO of Dune Networks. “By combining Dune’s industry leading SAND chipset with the LatticeSCM FPGA, we can provide a mutually beneficial solution to our customers at the lowest possible cost and footprint.”
“As demonstrated by our previously announced XAUI to SPI4.2 bridging solution, our LatticeSC™ and LatticeSCM FPGA devices are the ideal programmable platforms for Carrier Ethernet applications. We are very pleased to announce our cooperation with Dune Networks to provide a complete end to end packet fabric solution,” said Stan Kopec, Lattice corporate vice president of marketing.
When implemented in a LatticeSCM-15E FPGA in a space-saving 256 fine pitch Ball Grid Array (fpBGA) package, the Lattice XAUI to SPI4.2 bridging solution requires a mere 17mm x 17mm on a printed circuit board while consuming only 2.5Watts of power, substantially less than competitive devices.
SPAUI, an interface based on the XAUI industry standard, incorporates several extensions that provide 10Gbps applications with speedup (for packet headers, full rate 12GE), channelization, packet interleaving and refined flow control. SPAUI is implementation-friendly, backward compatible to standard XAUI and ideal for dense 10GE and higher speed Ethernet solutions. The SPAUI memorandum is available upon request from Dune Networks at no cost.
About Dune Networks
Dune Networks (www.dunenetworks.com) is a semiconductor supplier of networking devices that facilitate building Data Center, Enterprise and Carrier Ethernet switching solutions. The company’s products are scalable in system capacity, port rate and service scheme, offering a standard compliant, highly integrated and resilient architecture. Founded in 2000, Dune is located in Sunnyvale, California with an R&D center in the Europark Industrial Park at Yakum, Israel.
About the LatticeSC/M FPGA Family
The Extreme Performance™ LatticeSC family is designed to provide the unsurpassed performance and connectivity essential for high-speed applications. Fabricated on Fujitsu’s 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity. The LatticeSC family offers LUT counts up to 115K LUTs and 32 SERDES channels.
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8Gbps data rates, PURESPEED™ parallel I/O providing industry-leading 2Gbps speed, innovative clock management structures, FPGA logic operating at 500MHz and massive amounts of block RAM (up to 7.8 megabits of block RAM in a single device). Lattice’s unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as SPI4.2, Ethernet MAC and PCI Express control functions developed by Lattice to shorten end-system time to market.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices ( PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices ( CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.
Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com