Mentor Graphics Strengthens its SoC Leadership With New TeraPlace Physical Implementation Tool Suite
WILSONVILLE, Ore., April 17 -- Strengthening its leadership in the area of system-on-chip (SoC) design and verification, Mentor Graphics Corp. (Nasdaq: MENT) today introduced TeraPlace(TM), an innovative physical implementation tool suite developed to solve the critical time-to-market issues of timing closure and Deep Submicron (DSM) interconnect delay.
``TeraPlace not only marks Mentor's re-entry into the physical design market, it sets the standard for a new class of physical implementation tools,'' said Walden C. Rhines, president and CEO of Mentor Graphics Corp. ``By shifting the focus from traditional place and detail routing to the analysis and optimization of complex electrical effects deep within chip designs, the TeraPlace tool suite solves the problem of timing closure for DSM designs inherent in many existing tool flows.''
Extending traditional placement to include virtual routing, extraction with delay calculation, timing analysis and optimization, the Mentor Graphics® TeraPlace tool suite is comprised of TeraPlace, for innovative timing-driven placement and two plug-in options -- TeraOptimize(TM), for physical optimization and TeraCTS(TM), for Clock Tree Synthesis. By extending the traditional physical design link between placement and detailed routing, and providing accurate parasitic information earlier in the process, the tool suite delivers a highly integrated physical implementation solution that allows design teams to overcome the inconsistency of existing place and route solutions to reach timing closure.
Central to this success is the tool's ability to balance multiple design constraints such as timing, routability, area, wire length and signal integrity in an integrated solution built around incremental execution. By comparison, traditional placement products are based on outdated quadratic formulas developed for the submicron world. While these products provide excellent results when asked to optimize for a single design constraint, they break when faced with the complexity of today's SoC design starts.
TeraPlace Enhances Existing Design Flows
The TeraPlace tool suite's integrated physical implementation solution can easily be placed into a company's existing design flow. Built on de-facto standards, TeraPlace has already been proven successful at achieving timing closure with complex DSM designs from Actel, Centaur and Cyrix, a division of VIA Technologies, Inc.
``Not only did TeraPlace integrate seamlessly in our existing design flow, but our analysis showed that TeraPlace beats our previous placement tool in all situations,'' said Mark Brazell, CAD specialist at Centaur. ``Within a day of installing TeraPlace, we were building automated place and route blocks. The timing analysis tool integrated into TeraPlace was easy to use, produced meaningful timing reports and helped us achieve timing closure in record time.''
TeraPlace Reaches Timing Closure Where Other Tools Can't
The key to achieving timing closure is to focus on solving interconnect delays occurring during physical implementation with innovative placement. To do this, TeraPlace utilizes TeraSearch(TM), a highly adaptive placement algorithm to balance multiple design objectives including timing, routability and signal integrity. TeraPlace then verifies final placement with a virtual router that replaces inaccurate assumptions and estimations of wire load models with accurate parasitic data. Completing this process prior to detail routing represents the physical designer's best chance to optimize a design and avoid costly design iterations during the physical implementation phase.
TeraOptimize addresses changes that occur during optimization by supporting incremental design changes that can have a major impact on routability. These changes require that corresponding optimization changes be verified in context with the placement system. To do this, Mentor's Performance-based Incremental Placement(TM) (PIP(TM)) algorithm enhances standard placement by performing incremental placement that considers timing and signal integrity during physical optimization.
TeraCTS focuses on solving the complexity of DSM clock structures. Leveraging accurate resistance-capacitance (RC) data and a built-in timing analysis tool, clock trees are synthesized to minimize clock skew. This is all done with information provided from the TeraPlace placement system.
``With the complex design of the VIA Cyrix III processor, we needed a physical implementation solution that could reach timing closure quickly so that we could stay ahead of the market,'' stated Dr. David Hwang, physical layout CAD manager of the Cyrix division of VIA Technologies, Inc. ``By performing timing-driven layout with Mentor's TeraPlace PIP engine, we were able to quickly manage engineering change orders, resulting in proven silicon ahead of schedule.''
Capacity to Handle Multi-Million Gate Designs
Actel has already chosen TeraPlace as a standard part of the company's ProASIC design flow. ``Because of the design sizes and performance requirements faced by our customers designing ASIC-like programmable products (ProASIC), we have partnered with Mentor Graphics to include a custom version of the TeraPlace router as a standard part of Actel's ProASIC design flow,'' said Behrooz Zahiri, Actel's director of product marketing, software. ``Actel is very happy with the quality of placement being performed by TeraPlace from the standpoint of both the routability and performance achieved within our design flow.''
Pricing and Availability
Available immediately, Mentor's TeraPlace tool suite runs on the Unix operation system including Solaris and HP-UX. Pricing ranges from $50,000 to $200,000 for the complete solution of TeraPlace, TeraOptimize and TeraCTS.
About Mentor Graphics
Mentor Graphics Corp. is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $500 million and employs approximately 2,700 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.
NOTE: Mentor Graphics, TeraPlace, TeraOptimize, TeraCTS, TeraSearch, Performance-based Incremental Placement and PIP are registered trademarks and/or trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
CONTACT: Patti Atkins, Marketing Communications of Mentor Graphics Corp., 503-685-1165, or email@example.com; or Christian Bateman of Benjamin Group/BSMG Worldwide, 408-559-6090, or firstname.lastname@example.org, for Mentor Graphics Corp.