Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
SANTA CLARA, Calif. – November 5, 2007 – Tensilica, Inc. today unveiled the industry's smallest licensable 32-bit processor core based on an industry-standard architecture. The new Diamond Standard 106Micro core takes up only 0.26 mm 2 in a 130-nm G process and only 0.13 mm 2 in a 90-nm G process, which makes it smaller than the ARM7 or Cortex-M3 cores, yet at 1.22 Dhrystone MIPS/MHz, it delivers higher performance than the ARM9E cores.
The low-power Diamond Standard 106Micro is designed for simple controller applications in SOC (system-on-chip) designs, and an ideal choice for designers migrating from 8-bit and 16-bit microcontrollers to 32-bit processors. All Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners, who provide support with operating systems, design services, hardware prototyping and emulation, libraries and memories, EDA tools, and peripherals.
“In many SOC applications, the smallest possible microcontroller is all that's needed to coordinate the various tasks being performed on the chip,” explained Chris Rowen, Tensilica's president and CEO. “And often in devices that already have one or more other heavyweight applications processors on chip, one or more subsystems need a low-power, low-cost, localized controller. By leveraging our core configurable processor technology, we were able to quickly create this new core with the smallest footprint in the industry.”
The Diamond Standard 106Micro is an extremely low power, cache-less controller. It employs a 5-stage pipeline so it can easily achieve 250 MHz in 130G process and up to 400 MHz in 90G process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves a higher code density than other 32/16-bit architectures. Area and performance information for the Diamond 106Micro is in the chart below:
| ||130G ||90G ||65GP |
| ||Speed Opt ||Area Opt ||Speed Opt ||Area Opt ||Speed Opt ||Area Opt |
|Area (mm2) post-synthesis ||032 ||0.26 ||0.17 ||0.13 ||0.107 ||0.073 |
|Cell a rea (mm2) post-layout ||0.41 ||0.29 ||0.21 ||0.145 ||0.143 ||0.078 |
|Freq (MHz) post-layout ||250 ||125 ||400 ||200 ||610 ||300 |
|Power (mW/MHz) post-layout ||0.12 ||0.1 ||0.054 ||0.044 ||0.044 ||0.029 |
While it’s smaller and more area-efficient than other 32-bit commercial microcontrollers, the Diamond 106Micro is a fully equipped controller. Using a traditional Harvard architecture, it features separate local, tightly coupled, instruction and data RAMs to eliminate memory contention and provide fast performance on performance-critical code and interrupt handling routines. RAM size is user selectable up to 128K bytes. It features a 32-bit iterative multiplier for arithmetic operations, a trace port for debug, an integrated timer, and a rich interrupt architecture with 15 interrupts at two priority levels for flexible and fast interrupt handling.
The Diamond 106Micro offers performance comparable to other vendors’ much larger 32-bit CPUs in a smaller footprint. For example, the Diamond 106Micro core offers ARM9-level performance and capabilities in a smaller footprint than the ARM7 or Cortex M3 controllers. See table below:
| || |
AREA AND PERFORMANCE
| Max Frequency (0.13u G) worst case, Sage-X library, speed optimized || 160 MHz || 250 MHz || 135 MHz |
| Dhrystone MIPS || 152 || 305 || 169 |
| Area (0.13G) for base core (without bus interface, interrupt controller and timers) || 0.24 mm2 || 0.18 mm2 || 0.23 mm2 |
| mW per MHz (0.13G) Sage-X library, area optimized || 0.10 (does not include bus interface, interrupt controller, trace) || 0.1 || 0.12 (extrapolated from 0.84 using Metro libraries) |
| Pipeline stages || 3 || 5 || 3 |
| Code density || Mode bit to switch between 32- & 16-bit instructions || Modelessly switch between 24- and 16-bit instructions || Supports only ARM Thumb2 ISA |
| Memory architecture || Unified instruction and data interface || Separate instruction and data RAM TCMs || No TCMs |
| Interrupt controller || Needs external interrupt controller || Has integrated interrupt controller with 15 interrupts & 2 priority levels || Has optional interrupt controller |
| Number of integrated timers || 0 || 1 || 1 |
Data on ARM products taken from ARM public website and product information flyers, June 2007, for TSMC 0.13G process. All speed, power, and area metrics are subject to variation based on designer's design tools, libraries, and fab choices.
AMBA AHB-Lite and AXI Interfaces Available
All Tensilica Diamond Series cores are available with the native high-performance Tensilica PIF processor interface, suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect)
Additionally, designers can use the ARM AXI interface or the AMBA AHB-Lite interface to leverage existing infrastructure and peripheral component sets.
Based on Proven Xtensa Processor Technology
Tensilica’s entire Diamond Standard processor family is based on its proven Xtensa configurable and extensible processor architecture, used in over 250 chip designs by over 120 licensees. Tensilica’s engineers used the same Xtensa processor generator technology as its Xtensa processor customers use to create these optimized standard configurations. Tensilica’s automated processor generator technology completely verified the configurations and produced the matching software tool chain.
By using the proven Xtensa architecture, customers can be reassured that, if they like one of the Diamond Standard processors but would prefer a more tailored processor solution for their application, they can upgrade to an Xtensa configurable processor and maintain full software compatibility.
ASIC and Design Center Partner Support Demanded by Customers
Many ASIC customers prefer the simplicity of purchasing from their ASIC or foundry silicon provider a processor core as part of the NRE (Non-Recurring Engineering) expense of their SOC design. Fujitsu Microelectronics America, Inc. and NEC Electronics America, Inc. provide direct licensing of the Diamond Standard processors to their ASIC customers. And a network of Tensilica Authorized Design Centers around the world – including leading companies like AFTek, D-Clue, eInfochips, Genesis Technology, HD Lab, IBEX, Magellan Discovery Corp., Tallika, Tata Elxsi, and Wipro – can provide a Diamond Standard core as part of turnkey design services.
A Comprehensive Infrastructure of Tools and Peripheral Support
Tensilica provides a proven infrastructure for its Diamond Standard processor core family. This infrastructure includes software development tools directly from Tensilica as well as:
The Diamond 106Micro is supported by the ThreadX RTOS from Express Logic. The other members of the Diamond Standard processor series support not only ThreadX, but also Nucleus, uC/OS-II, open-source Linux, and micro-iTron.
Optional FPGA bitstream and board support package for Avnet Xilinx LX60 and LX200 demonstration boards
SOC emulation support from EVE, ProDesign, S2C, Sophia Systems, Synplicity, and Yokogawa Digital Computer
JTAG probe support from Bytetools, FS2, Macraigor Systems, and Sophia Systems
Libraries and memories from ARM (Artisan) and Virage Logic.
Support for popular EDA tools from Cadence, CoWare, Magma and Synopsys
Diamond 106Micro model for CoWare Platform Architect available from CoWare.
The Diamond Standard 106Micro is available now from Tensilica and its partners.
Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.