Silicon Efficient I/O Libraries Targeted For Mobile Consumer and Communications End EquipmentPLANO, Texas -- Nov. 5, 2007
-- Aragio Solutions (ARAGIO) announced today the immediate availability of silicon-proven I/O libraries for the 65-nanometer (nm) Common Platform technology process available from Chartered Semiconductor Manufacturing Ltd. This latest development extends the relationship between ARAGIO and Chartered, which has spanned numerous process technology nodes where Aragio's circuit techniques for high-frequency ESD and their use in competitive I/O library offerings have been silicon validated for manufacturing at Chartered. The breadth of programmable GPIO I/O, complex I/O and analog and mixed-signal intellectual property (IP) spans CMOS processes from 350nm to 65nm.
The 65nm programmable GPIO I/O library offering, augmented by a suite of specialty and system interface circuit I/O library pad sets, have been utilized by customers worldwide. ARAGIO developed the unique ESD protection and high latch-up immunity approach to be compatible with a full I/O library solution and provides IC designers with a selection of I/O library options available to design their entire ASIC/SoC I/O pad frame design. ARAGIO's innovative ESD protection and integrated circuit technology allows for silicon-efficient I/O libraries now being designed into many ASIC/SoC products.
"ARAGIO has been a valuable member of Chartered's ecosystem of design enablement providers, providing I/O solutions for Chartered's 180nm and 130nm processes. We have continued our relationship to include the Common Platform technology processes at 90nm and now at 65nm to provide chip designers with more advanced silicon-validated I/O library choices. ARAGIO's I/O libraries are fundamental building-blocks used in a number of customers' SoC devices," said Walter Ng, senior director of platform alliances at Chartered. "Chartered continues to work with ARAGIO to expand the support available for users of their I/O Library Solutions. Designers can take full advantage of ARAGIO's competitive offerings on Chartered's leading-edge manufacturing process technologies."
ARAGIO released a comprehensive set of 65nm programmable GPIO I/O libraries for both 2.5 V and 3.3 V operation. Each of these I/O libraries operates over a wide voltage range from 1.5 V to 2.5 V for the 2.5V I/O libraries and 1.8V to 3.3V for the 3.3V I/O libraries. The libraries include an extensive set of programmable and selectable features that include drive strength control, slew rate control and selectable input capability.
The I/O libraries are offered in staggered and a very silicon-efficient inline pad configuration. Furthermore, ARAGIO has released a robust offering of complex I/O library solutions including SSTL_2 Class I/II, SSTL_18, LVDS I/O, SubLVDS I/O, Ethernet MII/RMII driver, Ethernet GMII/RGMII driver, I2C driver, CE-ATA driver, USB 1.1, and USB 2.0 PHY Interface I/O library pads sets for the 65nm process. This 65-nm I/O library offering now provides a complete I/O library solution to enable a variety of product applications found in the consumer, communications, commercial data processing and home office computing environments.
"Our customers want to leverage their IP investments to enable early access use of 3rd Party IP with minimum risk. Chartered understands this and has an IP-friendly approach to customer sourcing needs. As a provider of silicon-efficient I/O library solutions, ARAGIO has successfully worked with many customers worldwide to help use our I/O libraries," said Robert L. ("Les") Veal, Sales and Marketing at ARAGIO. "From our perspective, the Chartered IP program provides an excellent process for validating and characterizing I/O library solutions on Chartered process technologies. Early silicon verification has helped us fulfill our mission to provide customers with high-quality, silicon-proven I/O library solutions. The customer, to accommodate a wider range of system interface feature content, can now improve their IP investment return by using the Programmable GPIO library to shift more feature capability under software control rather than investing in expensive release of separate ASIC designs."
ARAGIO's library deliverables include industry standard EDA tool views and models. ARAGIO's worldwide network of EDA, IP and design service partners extend the ARAGIO I/O Library Solutions capability to an impressive design enablement support for customers using the Common Platform technology 65nm CMOS process from Chartered.
ARAGIO's I/O library solutions in the Common Platform technology 65nm CMOS process technology from Chartered are available today with all metallization options supported by Chartered to qualified customers who have signed a license agreement.About Aragio Solutions
Aragio Solutions is recognized worldwide as a premier IP provider of innovative I/O Library Solutions, and has an excellent track record of silicon success by providing ESD protection solutions for I/O libraries used on numerous CMOS processes. ARAGIO has developed robust ESD protection and high latch-up immunity circuit techniques for System Interface Circuits enabling high performance operation for many industry standard interfaces (including USB 2.0 and DDR), RF and Analog ESD protection circuitry, as well as other high speed interface peripherals. ARAGIO's innovative integrated circuit technology allows for silicon-efficient I/O libraries found in many ASIC/SoC products. Contact ARAGIO at http://www.aragio.com