Optimised use of specific FPGA resources reduces costs power and size
Newport, Isle of Wight, UK – November 13, 2007 --
RF Engines Limited (RFEL), the specialists in high performance signal processing designs, has announced the availability of its latest ‘Vector Rotation/Translation’ IP core product. This core offers a sub-set of the features provided by the traditional CORDIC algorithm and dependant on the application, delivers significant savings in cost, power and size.‘CORDIC’
stands for CO
omputer and is an algorithm (or set of algorithms) that is frequently used in practical signal processing applications for calculating a wide range of mathematical functions including logarithmic, hyperbolic and trigonometric functions. The ‘CORDIC’
is commonly used, for example, in signal processing for radar systems, electronic warfare systems, and in linearisers for power amplifier designs.
algorithm has long been recognized and used in electronic systems design, but the continuing trend towards intensive signal processing on FPGA has revealed limitations in how to efficiently implement the design on FPGA devices and, more specifically, the ability to trade-off specific FPGA resources for its optimal implementation.
Typically, the CORDIC implementations that are generally available from mainstream FPGA vendors are heavily biased towards the use of the FPGA’s logic resources, compared with the use of the DSP and memory block resources. This heavy usage of the logic resources can often mean that, with a complex digital receiver front-end design, there are simply insufficient logic resources available in the FPGA to comfortably accommodate the logic-based CORDIC and still achieve the required FPGA clock rate.
The new RFEL ‘Vector Rotation/Translation’ CORDIC design addresses this issue and allows implementations which otherwise would be impracticable. The key innovation is in the design of the vector rotation for the polar-to-rectangular co-ordinate transformation and vice versa, and the RFEL approach utilises a proprietary technique to more efficiently exploit the appropriate FPGA resources.
The following example gives an idea of how this works in practice and compares a ‘conventional’ CORDIC with RFEL’s CORDIC for Vector Translation.
This example assumes a fairly typical specification of the following:
|Input width: || 20 bits |
|Magnitude width: || 20 bits |
|Phase width: || 12 bits |
|(Xilinx V5 Comparison) || 36K BRAMS || DSP48’s || Slices |
|Conventional CORDIC || 0 || 0 || 1669 |
|RFEL CORDIC || 3 || 2 || 274 |
As can be seen, the Slice count is now only 16% of the conventional design.
This approach has been successfully demonstrated in recent customer digital receiver designs, and the RFEL CORDIC has enabled the designs to be comfortably realised in a single FPGA, obviating the need for a second FPGA, and with the commensurate overall savings in system cost, size and power.
A parameterised Matlab model (pcode) is available for the new IP core. Although the above example is based on a Xilinx device, the core can be targeted at any FPGA device which supports both multipliers and block memory.
RF Engines Limited (RFEL) is a UK-based electronic systems designer, providing high specification signal processing solutions for FPGAs, as well as receiver and complete product solutions for the homeland security, defence, communications and instrumentation markets. Applications include communications base stations, satellite communications systems, test and measurement instrumentation, and bespoke wideband receivers/transceivers. www.rfel.com