New Products Deliver Greatly Improved Quality of Results for Datapath Design
SAN JOSE, CALIF. – November 20, 2007 – Arithmatica, the datapath design company, today announced the release of major updates to its flagship products CellMath Designer and CellMath IP. These new tools and intellectual property (IP) models set a new EDA industry standard for quality of results in datapath design through the implementation of innovative new algorithms, heuristics, and patented silicon math architectures.
Arithmatica is the only EDA company focused solely on datapath design automation to reduce power consumption, improve area utilization, and increase performance of datapath intensive ICs. Arithmatica’s tools and IP are useful for designing ICs used in 3D graphics, imaging, multimedia, wireline and wireless communications, high-performance computing, cryptography, storage and embedded processing applications. Arithmatica’s patented technology, accessible through its tools, IP and design services, provides differentiated product improvement and accelerated design cycles for datapath designers.
“We’re really excited about the new capability and quality of results we’re releasing in CellMath Designer and CellMath IP,” said Dan Ganousis, CEO of Arithmatica. “As IC designs transition to 65nm and smaller, datapath optimization is critical for reducing power and improving area utilization.”
CellMath Designer (CMD)
Datapath designs are becoming more than just math components as semiconductor companies continue to migrate towards configurable and platform IC designs. To address the trend of an increase in logic and multiplexer elements within datapath designs, Arithmatica has added new functionality to CMD that produces superior architectures and gate-level implementations. Built upon the foundation of Arithmatica’s patented A+ adder and Ax multiplier architectures, the new release of CMD offers unprecedented datapath synthesis capability at a fraction of the cost of logic synthesis tools from Synopsys and Cadence.
The quality of results from any synthesis tool is heavily dependent on the RTL coding style of the designer. CMD now performs “RTL transformations” automatically to produce an optimal internal design representation for its optimization engine. RTL transformations essentially are the embodiment of the knowledge and experience of Arithmatica’s mathematicians and design engineers who are experts in datapath design. Capturing their knowledge through heuristics and pattern matching algorithms, CMD can produce an optimal gate-level netlist without requiring users to manually adapt their Verilog RTL model for datapath synthesis.
CMD now also contains “mux synthesis” capability that automatically optimizes the implementation of multiplexers within the datapath. The new release of CMD merges multiplexers into higher-level structures and then optimizes them to meet the designer’s power, area, and delay requirements. CMD also features new algorithms for automatic carrysave insertion, local architectural selection, and new adder architectures that produce cooler, smaller, and faster datapath designs automatically.
While many vendors offer off-the-shelf IP for standard functions, Arithmatica provides customizable datapath IP using its collection of silicon-proven math building blocks. This is because in most advanced IC designs, all circuitry needs to be customized to reduce power, minimize area, and improve performance as much as possible. As designs move to 65 nm this becomes even more critical to address the significant increase in leakage and dynamic power. Arithmatica’s CellMath IP provides differentiated value through its IP customization services. Customers receive exactly the functionality they require without any of the additional overhead circuitry that is usually contained in off-the-shelf IP. Arithmatica has a long history of providing industry-leading IP, such as the DSP48 Slice contained within the Xilinx Virtex FPGA family, and continues to expand its catalog of datapath functions for graphics, networking, cryptography, and high-performance computing applications. Working from a customer’s functional specification and design constraints, Arithmatica returns a formally verified gate-level netlist that was created using CellMath IP building blocks along with bit-accurate simulation models. A customer receives all the benefits of a custom datapath IP solution but at a fraction of the cost and time required.
Pricing and Availability
CellMath Designer and CellMath IP are available immediately and support Verilog design flows. CellMath Designer pricing starts at US$19,999 for a Project Based License. CellMath IP pricing is dependent on the complexity of the datapath functionality required. Typical CellMath IP designs are priced at US$20,000 and are completed in 4-6 weeks.
Founded in 1998, Arithmatica is the leader in datapath design automation, providing software tools, IP, and consulting services to IC designers worldwide that allow them to automatically optimize their designs for power, area, and timing. Arithmatica is privately held with venture funding from SPARK Ventures (London) and NIF Ventures (Tokyo). Arithmatica’s products integrate seamlessly into existing IC design flows, supported through partnerships with Synopsys, Cadence, Magma, and Sequence Design. Arithmatica is headquartered in San Jose, Calif., with a research and development center in Warwick, U.K. For further information, please visit www.arithmatica.com.