Always-on Voice Activity Detection interfacing with analog microphones
Noesis Technologies Announces its Compact Area Parameterizable Reed Solomon Decoder and Encoder IP Core
November 26, 2007 -- Noesis Technologies today announced the immediate availability of its compact area parameterizable Reed Solomon Decoder and Encoder IP core (ntRS-CA). Along with its existing high throughput parameterizable Reed Solomon Decoder and Encoder (ntRS-HT), Noesis Technologies offers a complete portofolio of IP core solutions for applications that require error correction coding based on Reed Solomon algorithm.
The ntRS-HT and ntRS-CA IP cores are highly parameterizable and can be used in a variety of applications such as IEEE 802.16a, IEEE.802.16e, DVB-S, DVB-H, ITU G.984(GPON), ITU G.975, xDSL, IESS-308, CCSDS e.t.c.
The newly released ntRS-CA is especially ideal for low-power applications such DVB-H.
License options and availability
ntRS-CA is available under a flexible licensing scheme as parameterizable VHDL or Verilog source code or as a fixed netlist in various FPGA target technologies.
About Noesis Technologies
Noesis Technologies is a leading provider of Forward Error Correction IP core solutions. Noesis Technologies specializes in the design, development and marketing of high quality, cost effective communication IP cores and provides VLSI design services. Its field of expertise include Forward Error Correction, Cryptography and Networking technology. In these fields, a broad range of high quality IP cores are offered. Noesis IP cores have been licensed worldwide and its impressive list of customers ranges from large companies to dynamic startups in diverse market sectors such as telecommunications, networking, military, industrial control and lower-power portable. For more information, visit the Noesis website at www.noesis-tech.com.
|
Noesis Technologies Hot IP
Related News
- Noesis Technologies Releases DVB-H Reed Solomon Decoder
- intoPIX Releases a New Range of Compact Encoders and Decoders for JPEG XS
- AMPHION targets DAC 2016 to demonstrate compact HEVC/H.265 hardware decoder IP using H.265 bitstreams from encoder IP innovator NGCodec
- intoPIX Launches new compact JPEG2000 Encoder and Decoder FPGA IP-cores at ISE 2013
- eInfochips announces DDR2 SDRAM verification IP and Reed Solomon Encoder design IP
Breaking News
- Flex Logix and CEVA Announce First Working Silicon of a DSP with Embedded FPGA to Allow a Flexible/Changeable ISA
- sureCore's ultra-low memory technologies enable designers to create the reality of the metaverse
- IAR Systems enable Visual Studio Code extensions to meet developer demands
- TSMC Japan 3DIC R&D Center Completes Clean Room Construction in AIST Tsukuba Center
- Ansys Multiphysics Solutions Achieve Certification for TSMC's N3E and N4P Process Technologies
Most Popular
- MosChip Technologies Appoints Semiconductor Industry Veteran, DVR Murthy As "Vice President of Strategic Initiatives" to Implement and Execute Expanded Solution Offerings
- Imagination launches IMG RTXM-2200 - its first real-time embedded RISC-V CPU
- TSMC Creates Design Options for New 3nm Node
- Intento Design Secures Third Round of Investment to Accelerate Its Commercial Deployment
- GlobalFoundries Celebrates New Singapore Fab with Arrival of First Tool
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |