Hoping to establish programmable logic as a viable platform for mainstream DSP applications, Xilinx Inc. has developed what it hopes will be the missing link between system-level modeling and FPGA hardware design.
While reconfigurability has made FPGAs a natural target for prototyping DSP designs, the laborious process of hardware translation has dulled their time-to-market edge compared with custom silicon or off-the-shelf processors.
At the DSP World conference in San Jose this week, Xilinx will demonstrate the first fruit of an exclusive alliance with leading DSP tool developer The MathWorks Inc. Known as the Xilinx System Generator for the MathWorks Simulink Interface, the tool is aimed at eliminating the line-by-line hand-coding and reiterations that today account for at least a third of the DSP design cycle.
Xilinx is readying a beta version of the tool, and anticipates a formal release in the third quarter.
PLD suppliers a few yea rs ago began promoting their chips as a fast and flexible way to run finite state-machine-type DSP algorithms-offering more computing power than DSP chips but without the high cost and long design cycles of ASICs. Xilinx and rival Altera Corp. have been the most vocal proponents of the concept, and market watchers said they've made good headway by developing IP cores and industry alliances to further the cause. However, all efforts to date have focused on either high-level DSP modeling or hardware issues-not the gap in between, said Per Holmberg, marketing manager of IP Solutions at Xilinx, San Jose.
"The question we kept getting from customers was, 'Okay, we're convinced; now how do we use it?'" Holmberg said. "They couldn't see a bridge from C-language [models] to hardware."
Xilinx's System Generator tool is designed to be the bridge, seamlessly linking MathWorks' Simulink System-Level Design Environment with its own Foundation and Alliance tools to automatically translate C-language algorithms int o VHDL source code. Within the FPGA design environments, the System Generator will work with Xilinx's CORE Generator to produce highly optimized versions of the company's DSP cores. In the end, verification of the design is also simplified, Xilinx said.
The result is appealing on many levels, said Steve Farley, a hardware engineer at Scientific Atlanta's Media Networks division in Toronto, which has agreed to be a beta site for the System Generator. More than simply offering time savings, Farley said the tool will allow designers to make important decisions about cost and performance earlier in the design cycle.
"Let's say you're designing a system with a bunch of digital filters. You can experiment with the behavior of the filters up front, and very quickly get an estimate of how much [logic] resources will be required before converting the design into code," he said. "This way, you can do some algorithmic trade-offs between performance and [silicon] area sooner to see how much it will cost to build and how much faster it will run, compared to an off-the-shelf DSP running software."
FPGAs have become increasingly important in DSP designs, though they are most often used to run specialized algorithms in parallel with conventional DSP chips, according to Will Strauss of Forward Concepts Co., Tempe, Ariz.
In 1999, approximately $70 million worth of FPGAs were employed to execute DSP algorithms, Strauss said. While that might seem miniscule compared with the $4.4 billion DSP market, FPGA-based DSPs are expected to grow at least as quickly. Strauss forecasts worldwide DSP revenue to rise 40% this year.
Much of the momentum in FPGAs will come from new applications in wide-area networks, HDTV, and cellular base stations. In CDMA networks, for example, FPGAs are being used for high-speed Turbo coding and spectrum spread/despread.
"Traditional DSPs have not been fast enough to do this up to now," Strauss said. "The fact is, FPGAs are getting cheaper, and the volume-we're talking 35,000 base stat ions a year-is such that FPGAs make a lot of sense."
The reconfigurable aspect of the devices becomes valuable during the code-translation stage, allowing a fast and inexpensive design reiteration, whereas an ASIC implementation would cost millions of dollars in mask sets, and add months to the design cycle. Additionally, FPGA silicon can be surprisingly more powerful than a DSP chip.
With an FPGA, designers can make a lot of simple circuits in parallel, and achieve extremely high computation speeds.
And silicon performance increases with gate density, according to Babak Hedayati, director of IP marketing and business development at Xilinx.
"We're hitting 64 billion MACs [multiply and accumulates] with our existing products," he said. "The fastest DSP today does maybe 1 billion."